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Synthesis of timing paths with delays adaptable to integrated circuit variability
| dc.contributor | Cortadella, Jordi |
| dc.contributor.author | Moreno Vega, Alberto |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
| dc.date.accessioned | 2015-12-23T14:44:14Z |
| dc.date.available | 2015-12-23T14:44:14Z |
| dc.date.issued | 2015-07-10 |
| dc.identifier.uri | http://hdl.handle.net/2117/81051 |
| dc.description.abstract | This project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce variability guard band margins at design stage. |
| dc.language.iso | eng |
| dc.publisher | Universitat Politècnica de Catalunya |
| dc.subject | Àrees temàtiques de la UPC::Informàtica |
| dc.subject.lcsh | Integrated circuits |
| dc.subject.other | variabilitat |
| dc.subject.other | camí crític |
| dc.subject.other | process corner |
| dc.subject.other | beam search |
| dc.subject.other | ring oscillator |
| dc.subject.other | rellotges adaptatius |
| dc.subject.other | llibreria de standard cells |
| dc.subject.other | Variability |
| dc.subject.other | critical path |
| dc.subject.other | process corner |
| dc.subject.other | adaptive clocks |
| dc.subject.other | standard cell library |
| dc.title | Synthesis of timing paths with delays adaptable to integrated circuit variability |
| dc.type | Master thesis |
| dc.subject.lemac | Circuits integrats |
| dc.identifier.slug | 109546 |
| dc.rights.access | Open Access |
| dc.date.updated | 2015-07-14T04:00:29Z |
| dc.audience.educationlevel | Màster |
| dc.audience.mediator | Facultat d'Informàtica de Barcelona |
| dc.audience.degree | MÀSTER UNIVERSITARI EN INNOVACIÓ I RECERCA EN INFORMÀTICA (Pla 2012) |
