Enviaments recents

  • Monitoring strategies for scalable dynamic checkpointing 

    Perarnau, Swann; Bautista-Gomez, Leonardo (Institute of Electrical and Electronics Engineers (IEEE), 2017-04-06)
    Comunicació de congrés
    Accés obert
    Resilience is an important challenge for extreme-scale supercomputers. Failures in current supercomputers are assumed to be uniformly distributed in time. However, recent studies show that failures in high-performance ...
  • Database Integrated Analytics Using R: Initial Experiences with SQL-Server + R 

    Berrall, Josep Ll.; Poggi, Nicolas (Institute of Electrical and Electronics Engineers (IEEE), 2017-02-02)
    Comunicació de congrés
    Accés obert
    Most data scientists use nowadays functional or semi-functional languages like SQL, Scala or R to treat data, obtained directly from databases. Such process requires to fetch data, process it, then store again, and such ...
  • A runtime heuristic to selectively replicate tasks for application-specific reliability targets 

    Subasi, Omer; Yalcin, Gulay; Zyulkyarov, Ferad; Unsal, Osman Sabri; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés obert
    In this paper we propose a runtime-based selective task replication technique for task-parallel high performance computing applications. Our selective task replication technique is automatic and does not require ...
  • A static scheduling approach to enable safety-critical OpenMP applications 

    Melani, Alessandra; Serrano, Maria A.; Bertogna, Marko; Cerutti, Isabella; Quiñones, Eduardo; Buttazzo, Giorgio (IEEE, 2017-02-20)
    Text en actes de congrés
    Accés obert
    Parallel computation is fundamental to satisfy the performance requirements of advanced safety-critical systems. OpenMP is a good candidate to exploit the performance opportunities of parallel platforms. However, safety-critical ...
  • Measurement-based timing analysis of the AURIX caches 

    Kosmidis, Leonidas; Compagnin, Davide; Morales, David; Mezzetti, Enrico; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
    Text en actes de congrés
    Accés obert
    Cache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has ...
  • TaskInsight: Understanding Task Schedules Effects on Memory and Performance 

    Ceballos, Germán; Grass, Thomas; Hugo, Andra; Black-Schaffer, David (Association for Computing Machinery, 2017-02)
    Text en actes de congrés
    Accés obert
    Recent scheduling heuristics for task-based applications have managed to improve their by taking into account memory-related properties such as data locality and cache sharing. However, there is still a general lack of ...
  • REPP-H: runtime estimation of power and performance on heterogeneous data centers 

    Nishtala, Rajiv; Martorell Bofill, Xavier; Petrucci, Vinicius; Mossé, Daniel (2016)
    Text en actes de congrés
    Accés obert
    Modern data centers increasingly demand improved performance with minimal power consumption. Managing the power and performance requirements of the applications is challenging because these data centers, incidentally or ...
  • A confidence assessment of WCET estimates for software time randomized caches 

    Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés obert
    Obtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates ...
  • Rebalancing the core front-end through HPC code analysis 

    Milic, Ugljesa; Carpenter, Paul; Rico, Alejandro; Ramirez, Alex (IEEE, 2016-10-10)
    Text en actes de congrés
    Accés obert
    There is a need to increase performance under the same power and area envelope to achieve Exascale technology in high performance computing (HPC). The today's chip multiprocessor (CMP) design is tailored by traditional ...
  • A Review of Lightweight Thread Approaches for High Performance Computing 

    Castelló, Adrián; Peña, Antonio J.; Seo, Sangmin; Mayo, Rafael; Balaji, Pavan; Quintana-Ortí, Enrique S. (IEEE, 2016-12-08)
    Text en actes de congrés
    Accés obert
    High-level, directive-based solutions are becoming the programming models (PMs) of the multi/many-core architectures. Several solutions relying on operating system (OS) threads perfectly work with a moderate number of ...

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