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Tareador: a tool to unveil parallelization strategies at undergraduate level
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Badia Sala, Rosa Maria |
dc.contributor.author | Jiménez González, Daniel |
dc.contributor.author | Herrero Zaragoza, José Ramón |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Subotic, Vladimir |
dc.contributor.author | Utrera Iglesias, Gladys Miriam |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2015-12-11T14:34:13Z |
dc.date.available | 2015-12-11T14:34:13Z |
dc.date.issued | 2015 |
dc.identifier.citation | Ayguade, E., Badia, R.M., Jimenez, D., Herrero, J., Labarta, J., Subotic, V., Utrera, G. Tareador: a tool to unveil parallelization strategies at undergraduate level. A: Workshop on Computer Architecture Education. "Workshop on computer architecture education held in conjunction with 42nd International Symposium on Computer Architecture". Portland: North Carolina State University, 2015. |
dc.identifier.uri | http://hdl.handle.net/2117/80429 |
dc.description.abstract | This paper presents a methodology and framework designed to assist students in the process of finding appropriate task decomposition strategies for their sequential program, as well as identifying bottlenecks in the later execution of the parallel program. One of the main components of this framework is Tareador, which provides a simple API to specify potential task decomposition strategies for a sequential program. Once the student proposes how to break the sequential code into tasks, Tareador 1) provides information about the dependences between tasks that should be honored when implementing that task decomposition using a parallel programming model; and 2) estimates the potential parallelism that could be achieved in an ideal parallel architecture with infinite processors; and 3) sim- ulates the parallel execution on an ideal architecture estimating the potential speed–up that could be achieved on a number of processors. The pedagogical style of the methodology is currently applied to teach parallelism in a third-year compulsory subject in the Bachelor Degree in Informatics Engineering at the Barcelona School of Informatics of the Universitat Politècnica de Catalunya (UPC) - BarcelonaTech. |
dc.language.iso | eng |
dc.publisher | North Carolina State University |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Computer architecture |
dc.title | Tareador: a tool to unveil parallelization strategies at undergraduate level |
dc.type | Conference report |
dc.subject.lemac | Arquitectura d'ordinadors |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://www.ncsu.edu/wcae/ISCA2015/papers/p1-ayguade.pdf |
dc.rights.access | Open Access |
local.identifier.drac | 16271595 |
dc.description.version | Postprint (published version) |
local.citation.author | Ayguade, E.; Badia, R.M.; Jimenez, D.; Herrero, J.; Labarta, J.; Subotic, V.; Utrera, G. |
local.citation.contributor | Workshop on Computer Architecture Education |
local.citation.pubplace | Portland |
local.citation.publicationName | Workshop on computer architecture education held in conjunction with 42nd International Symposium on Computer Architecture |