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dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorBadia Sala, Rosa Maria
dc.contributor.authorJiménez González, Daniel
dc.contributor.authorHerrero Zaragoza, José Ramón
dc.contributor.authorLabarta Mancho, Jesús José
dc.contributor.authorSubotic, Vladimir
dc.contributor.authorUtrera Iglesias, Gladys Miriam
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2015-12-11T14:34:13Z
dc.date.available2015-12-11T14:34:13Z
dc.date.issued2015
dc.identifier.citationAyguade, E., Badia, R.M., Jimenez, D., Herrero, J., Labarta, J., Subotic, V., Utrera, G. Tareador: a tool to unveil parallelization strategies at undergraduate level. A: Workshop on Computer Architecture Education. "Workshop on computer architecture education held in conjunction with 42nd International Symposium on Computer Architecture". Portland: North Carolina State University, 2015.
dc.identifier.urihttp://hdl.handle.net/2117/80429
dc.description.abstractThis paper presents a methodology and framework designed to assist students in the process of finding appropriate task decomposition strategies for their sequential program, as well as identifying bottlenecks in the later execution of the parallel program. One of the main components of this framework is Tareador, which provides a simple API to specify potential task decomposition strategies for a sequential program. Once the student proposes how to break the sequential code into tasks, Tareador 1) provides information about the dependences between tasks that should be honored when implementing that task decomposition using a parallel programming model; and 2) estimates the potential parallelism that could be achieved in an ideal parallel architecture with infinite processors; and 3) sim- ulates the parallel execution on an ideal architecture estimating the potential speed–up that could be achieved on a number of processors. The pedagogical style of the methodology is currently applied to teach parallelism in a third-year compulsory subject in the Bachelor Degree in Informatics Engineering at the Barcelona School of Informatics of the Universitat Politècnica de Catalunya (UPC) - BarcelonaTech.
dc.language.isoeng
dc.publisherNorth Carolina State University
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshComputer architecture
dc.titleTareador: a tool to unveil parallelization strategies at undergraduate level
dc.typeConference report
dc.subject.lemacArquitectura d'ordinadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://www.ncsu.edu/wcae/ISCA2015/papers/p1-ayguade.pdf
dc.rights.accessOpen Access
local.identifier.drac16271595
dc.description.versionPostprint (published version)
local.citation.authorAyguade, E.; Badia, R.M.; Jimenez, D.; Herrero, J.; Labarta, J.; Subotic, V.; Utrera, G.
local.citation.contributorWorkshop on Computer Architecture Education
local.citation.pubplacePortland
local.citation.publicationNameWorkshop on computer architecture education held in conjunction with 42nd International Symposium on Computer Architecture


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