Els avenços recents en tecnologies de fabricació electròniques han permès augmentar el grau d'integració dels circuits que realitzen funcions altament complexes a baix cost. A més, les prestacions segueixen creixent a ritme accelerat, tendència que es mantindrà en la propera dècada segons les previsions de l?International Roadmap for Semiconductors (IRS). L'objectiu general del grup és aconseguir avançar en noves metodologies de disseny de circuits i sistemes electrònics i millorar-ne la qualitat assegurant-ne el funcionament correcte. En concret, un dels objectius se centra a millorar les tècniques de disseny de baix consum en tecnologies CMOS nanomètriques. En l'àmbit de millora de la qualitat de funcionament de circuits i sistemes, els objectius se centren a millorar les tècniques de test i autotest en circuits i sistemes analògics, digitals i mixtos. Finalment, un tercer objectiu tracta de millorar la qualitat de funcionament "tolerant les fallades" que puguin escapar de les metodologies de test de circui

http://futur.upc.edu/QINE

Recent advances in the manufacture of electronic circuits have enabled an increase in the integration levels of integrated circuits (ICs), which currently perform highly complex functions at a low cost. In addition, the performance of these ICs is steadily increasing and, according to the International Roadmap for Semiconductors (IRS), this trend is expected to continue during the coming decade. The general aim of the research group is to make advances in new design methodologies for electronic circuits and systems, and to increase their quality by ensuring their correct functionality. The objectives of the research are threefold: to make advances in design techniques for low-power circuits in nanometric CMOS technologies; to innovate in testing and auto-testing methods for analogue, digital and mixed-signal circuits; and to devise techniques that enhance functionality, by means of the tolerance of faults that might escape standard circuit and system testing methods.

http://futur.upc.edu/QINE

Recent advances in the manufacture of electronic circuits have enabled an increase in the integration levels of integrated circuits (ICs), which currently perform highly complex functions at a low cost. In addition, the performance of these ICs is steadily increasing and, according to the International Roadmap for Semiconductors (IRS), this trend is expected to continue during the coming decade. The general aim of the research group is to make advances in new design methodologies for electronic circuits and systems, and to increase their quality by ensuring their correct functionality. The objectives of the research are threefold: to make advances in design techniques for low-power circuits in nanometric CMOS technologies; to innovate in testing and auto-testing methods for analogue, digital and mixed-signal circuits; and to devise techniques that enhance functionality, by means of the tolerance of faults that might escape standard circuit and system testing methods.

http://futur.upc.edu/QINE

Enviaments recents

  • Improving indirect test efficiency using multi-directional tessellations in the measure space 

    Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
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    Indirect test strategies have risen as a promising solution to overcome the challenges encountered in analog and mixed-signal circuit testing and the ever increasing device verification costs. This work explores the ...
  • RRAM based cell for hardware security applications 

    Arumi Delgado, Daniel; Manich Bou, Salvador; Rodríguez Montañés, Rosa (2016)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Resistive random access memories (RRAMs)have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. ...
  • Test escapes of stuck-open faults caused by parasitic capacitances and leakage currents 

    Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras, Joan (2015-09-24)
    Article
    Accés obert
    Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled ...
  • Backside polishing detector: a new protection against backside attacks 

    Manich Bou, Salvador; Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Mujal Colell, Jordi; Hernández García, David (2015)
    Text en actes de congrés
    Accés obert
    Secure chips are in permanent risk of attacks. Physical attacks usually start removing part of the package and accessing the dice by different means: laser shots, electrical or electromagnetic probes, etc. Doing this ...
  • Efficient production binning using octree tessellation in the alternate measurements space 

    Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan (2015)
    Article
    Accés obert
    Binning after volume production is a widely accepted technique to classify fabricated ICs into different clusters depending on different degrees of specification compliance. This allows the manufacturer to sell non optimal ...
  • Mixed-signal test band guarding using digitally coded indirect measurements 

    Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using ...
  • Power-aware voltage tuning for STT-MRAM reliability 

    Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Di Carlo, Stefano; Renovell, Michel; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Text en actes de congrés
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    One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. ...
  • Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell 

    Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Indaco, Marco; Renovell, Michel; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin- Transfer-Torque ...
  • STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations 

    Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Indaco, Marco; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Text en actes de congrés
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    The CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. ...
  • Defeating simple power analysis attacks in cache memories 

    Neagu, Madalin; Manich Bou, Salvador; Miclea, Liviu (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    A wide range of attacks that target cache memories in secure systems have been reported in the last half decade. Cold-boot attacks can be thwarted through the recently proposed Interleaved Scrambling Technique (IST). ...

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