Mirs: modulo scheduling with integrated register spilling
Tipus de documentArticle
Condicions d'accésAccés restringit per política de l'editorial
The overlapping of loop iterations in software pipelining techniques imposes high register requirements. The schedule for a loop is valid if it requires at most the number of registers available in the target architecture. Otherwise its register requirements have to be reduced by spilling registers to memory. Previous proposals for spilling in software pipelined loops require a two-step process. The first step performs the actual instruction scheduling without register constraints. The second step adds (if required) spill code and reschedules the modified loop. The process is repeated until a valid schedule, requiring no more registers than those available, is found. The paper presents MIRS (Modulo scheduling with Integrated Register Spilling), a novel register-constrained modulo scheduler that performs modulo scheduling and register spilling simultaneously in a single step. The algorithm is iterative and uses backtracking to undo previous scheduling decisions whenever resource or dependence conflicts appear. MIRS is compared against a state-of-the-art two-step approach already described in the literature. For this purpose, a workbench composed of a large set of loops from the Perfect Club and a set of processor configurations are used. On the average, for the loops that require spill code a speed-up in the range 14–31% and a reduction of the memory traffic by a factor in the range 0.90–0.72 are achieved.
CitacióZalamea, F., Llosa, J., Ayguade, E., Valero, M. Mirs: modulo scheduling with integrated register spilling. "Lecture notes in computer science", Gener 2003, vol. 2624, p. 239-253.
Versió de l'editorhttp://link.springer.com/chapter/10.1007%2F3-540-35767-X_16
|MIRS Modulo Sch ... ated Register Spilling.pdf||MIRS Modulo Scheduling with Integrated Register Spilling||293.3Kb||Accés restringit|