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Resistive open defect characteritzation in 3D 6T SRAM memories
dc.contributor.author | Castillo, Raúl |
dc.contributor.author | Arumi Delgado, Daniel |
dc.contributor.author | Rodríguez Montañés, Rosa |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2015-10-14T14:41:39Z |
dc.date.issued | 2014 |
dc.identifier.citation | Castillo, R., Arumi, D., Rodriguez, R. Resistive open defect characteritzation in 3D 6T SRAM memories. A: Conference on Design of Circuits and Integrated Systems. "Proceedings XXIX Conference on Design of Circuits and Integrated Systems". Madrid: 2014, p. 1-6. |
dc.identifier.uri | http://hdl.handle.net/2117/77724 |
dc.description.abstract | The relentless decrease in feature size and the increase of density requirements in Integrated Circuit (IC) manufacturing arise new challenges that must be overcome. One of the most promising alternatives is three-dimensional integrated circuits (3D ICs). Several possibilities have been presented, but one of the clearest options is based on the use of Though-Silicon Vias (TSV) connections. The benefits and disadvantages that TSV inclusion adds to design need further studies. The implementation of these vertical vias can affect the general performance of circuit and thus changing verification strategies or testing processes. In this paper, the electrical effect of open defects affecting TSVs in a 3D SRAM module is presented. Analytical expressions are presented to provide designers a tool to improve circuit features and help them in the analysis of how TSV implementation can affect a SRAM array design |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Modeling |
dc.title | Resistive open defect characteritzation in 3D 6T SRAM memories |
dc.type | Conference report |
dc.subject.lemac | Modelatge -- Congressos |
dc.contributor.group | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 16869594 |
dc.description.version | Postprint (author’s final draft) |
dc.date.lift | 10000-01-01 |
local.citation.author | Castillo, R.; Arumi, D.; Rodriguez, R. |
local.citation.contributor | Conference on Design of Circuits and Integrated Systems |
local.citation.pubplace | Madrid |
local.citation.publicationName | Proceedings XXIX Conference on Design of Circuits and Integrated Systems |
local.citation.startingPage | 1 |
local.citation.endingPage | 6 |