Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences that tasks suffer when accessing shared hardware resources.We propose an analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard real-time CMPs, that reduces the impact of memory interferences caused by other tasks on WCET estimation, providing a predictable memory access time and allowing the computation of
tight WCET estimations.
CitationPaolieri, M. [et al.]. An analyzable memory controller for hard real-time CMPs. "Ieee EMBEDDED SYSTEMS LETTERS", 05 Febrer 2010, vol. 1, núm. 4, p. 86-90.
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