Recent Submissions

  • Advanced failure detection techniques in deep submicron CMOS integrated circuits 

    Rubio Sola, Jose Antonio; Altet Sanahujes, Josep; Mateo Peña, Diego (Pergamon Press, 2009)
    Conference report
    Restricted access - publisher's policy
    The test of present integrated circuits exhibits many confining aspects, among them the adequate selection of the observable variables, the use of combined testing approaches, an each time more restricted controllability ...
  • A crosstalk latch circuit design 

    Rubio Sola, Jose Antonio; Pons Nin, Joan; Anglada, Raimon (Institute of Electrical and Electronics Engineers (IEEE), 1990)
    Conference report
    Restricted access - publisher's policy
    A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range ...
  • Asynchronous pulse logic cell for threshold logic and Boolean networks 

    Lambie, J; Moll Echeto, Francisco de Borja; González Jiménez, José Luis; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Restricted access - publisher's policy
    In this article, a fully digital CMOS circuit for asynchronous pulse cells is presented. The proposed circuit has a high noise tolerance and no static power consumption. Furthermore it has a high functional programmability. ...
  • High level spectral-based análisis of power concumption in DSP's systems 

    Calomarde Palomino, Antonio; Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2006)
    Conference report
    Restricted access - publisher's policy
    In this paper, an efficient technique to evaluate temporal correlation and transition activity at high level in DSP systems is presented. The method is based on the spectral distribution of signals and has the advantage ...
  • Statistical Lifetime Analysis in Memristive Crossbar 

    Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2015)
    Conference report
    Open Access
    Emerging devices for future memory technologies have attracted great attention recently. Memristors are one of the most favorable such devices, due to their high scalability and compatibility with CMOS fabrication process. ...
  • Proactive reconfiguration, a methodology for extending SRAM lifetime 

    Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2012)
    Conference lecture
    Restricted access - publisher's policy
    The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems with embedded SRAM cells. This work introduces a novel version that modifies and enhances the advantages of this technique ...
  • Characterization of random telegraph noise and its impact on reliability of SRAM sense amplifiers 

    Martín Martínez, Javier; Diaz, Javier; Rodríguez, Rosana; Nafria, Montse; Aymerich Humet, Xavier; Roca Moreno, Elisenda; Fernández Fernández, Francisco V.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Open Access
    A new method for the analysis of multilevel Random Telegraph Noise (RTN) signals has been recently presented, which can also be applied in the case of large background noise. In this work, the method is extended to evaluate ...
  • All-digital self-adaptive PVTA variation aware clock generation system for DFS 

    Pérez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja (2014)
    Conference report
    Open Access
    An all-digital self-adaptive clock generation system capable of adapt the clock frequency to compensate the effects of PVTA variations on the IC propagation delay and satisfy an externally set propagation length condition ...
  • iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Open Access
    Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical ...
  • Variability impact on on-chip memory data paths 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2014)
    Conference lecture
    Open Access
    Process variations have a large impact on device and circuit reliability and performance. Few studies are focused on their impact on more complex systems, as for example their influence in a data path. In our study, the ...

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