Enviaments recents

  • FastIC: a fast integrated circuit for the readout of high performance detectors 

    Gómez Fernández, Sergio; Alozy, J.; Campbell, Michael; Manera Escalero, Rafael; Mauricio Ferré, Juan; Sanmukh, Anand; Sanuy Charles, Andreu; Ballabriga, Rafael; Gascón Fora, David (2022-05-01)
    Article
    Accés obert
    This work presents the 8-channel FastIC ASIC developed in CMOS 65¿nm technology suitable for the readout of positive and negative polarity sensors in high energy physics experiments, Cherenkov detectors and time-of-flight ...
  • VCO phase noise and sideband spurs due to substrate noise generated by on-chip digital circuits 

    Méndez Villegas, Miguel Ángel; Osorio Tamayo, Juan Felipe; Mateo Peña, Diego; Aragonès Cervera, Xavier; González Jiménez, José Luis (Institute of Electrical and Electronics Engineers (IEEE), 2006)
    Text en actes de congrés
    Accés obert
    This paper presents the effects of noise generated by realistic digital circuits on RF voltage controlled oscillators (VCO) integrated in the same silicon die. The digital noise is coupled through the common substrate and ...
  • Frequency characterization of a 2.4 GHz CMOS LNA by Thermal Measurements 

    Mateo Peña, Diego; Altet Sanahujes, Josep; Aldrete Vidrio, Héctor; González Jiménez, José Luis (Institute of Electrical and Electronics Engineers (IEEE), 2006)
    Text en actes de congrés
    Accés obert
    This paper presents a technique to obtain electrical characteristics of analog and RF circuits, based on measuring temperature at the silicon surface close to the circuit under test. Experimental results validate the ...
  • Using temperature as observable of the frequency response of RF CMOS amplifiers 

    Aldrete Vidrio, Héctor; Slhi, M A; Altet Sanahujes, Josep; Gruby, S; Mateo Peña, Diego; Michel, H; Clerjaud, L; Rampnous, J M; Rubio Sola, Jose Antonio; Claeys, Wilfrid; Dilhaire, W Claeys I S (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Text en actes de congrés
    Accés obert
    The power dissipated by the devices of an integrated circuit can be considered a signature of the circuit's performance. Without disturbing the circuit operation, this power consumption can be monitored by temperature ...
  • A low-power RF front-end for 2.5 GHz receivers 

    Moreno Boronat, Lidia Ana; Gómez, D; González Jiménez, José Luis; Mateo Peña, Diego; Aragonès Cervera, Xavier; Berenguer, R; Solar, H (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Text en actes de congrés
    Accés obert
    This paper presents a low power and low cost front end for a direct conversion 2.5 GHz ISM band receiver composed of a 16 kV HBM ESD protected LNA, differential Gilbert-cell mixers, and high-pass filters for DC offset ...
  • Design and implementation of a 5/spl times/5 trits multiplier in a quasi-adiabatic ternary CMOS logic 

    Mateo Peña, Diego; Rubio Sola, Jose Antonio (1998-07)
    Article
    Accés obert
    Adiabatic switching is a technique to design low-power digital IC's. Fully adiabatic logics have expensive silicon area requirements. To solve this drawback, a quasi-adiabatic ternary logic is proposed. Its basis is ...
  • An approach to dynamic power consumption current testing of CMOS ICs 

    Segura, J A; ROCA, M; Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 1995)
    Text en actes de congrés
    Accés obert
    I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can ...
  • Implementation of a 5x5 trits multiplier in a quasi-adiabatic ternary CMOS logic 

    Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Text en actes de congrés
    Accés obert
    Adiabatic switching is one technique to design low power digital IC. In order to diminish its expensive silicon area requirements an adiabatic ternary logic is proposed. A 5×5 trits (ternary signals) multiplier has been ...
  • Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design 

    Rullán Ayza, Mercedes; Ferrer Ramis, Carles; Oliver, Joan; Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 1996)
    Text en actes de congrés
    Accés obert
    Difference between ISSQ and IDDQ testing strategies is presented, discussing the dependency of area overhead and sensing speed on the technology. The current sensor implementation style suitable for cell-based design ...
  • Characterization of the substrate noise spectrum for mixed-signal ICs 

    Méndez Villegas, Miguel Ángel; Mateo Peña, Diego; Rubio Sola, Jose Antonio; González Jiménez, José Luis (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Text en actes de congrés
    Accés obert
    This paper presents a simplified analytical model of the substrate noise generated by digital circuitry that captures the most relevant frequency domain characteristics and relates them with parameters of the digital circuit ...
  • Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact 

    Calomarde Palomino, Antonio; Manich Bou, Salvador; Rubio Sola, Jose Antonio; Gamiz, Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2022-05-02)
    Article
    Accés obert
    This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 ...
  • CMOS inverter performance degradation and its correlation with BTI, HCI and OFF state MOSFETs aging 

    Crespo Yepes, Albert; Nasarre Campo, Carles; Garsot Borras, Norbert; Martin Martínez, Javier; Rodríguez Martínez, Rosana; Barajas Ojeda, Enrique; Aragonès Cervera, Xavier; Mateo Peña, Diego; Nafría Maqueda, Montserrat (2022-05-01)
    Article
    Accés restringit per política de l'editorial
    In this work, CMOS inverters are subjected to electrical stress emulating a complete operation cycle and the shifts in the performance parameters (i.e., peak current and inversion voltage) evaluated. Moreover, degradation ...

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