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Interleaved Scrambling Technique: A Novel Low-Power Security Layer for Cache Memories
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
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Memory systems security has increased over the last decade due to the sensitive information which is stored in plain text. Device specific attacks, such as cold-boot and sidechannel monitoring have been reported as being ...
A comparison of numerical splitting-based methods for Markovian dependability and performability models
(Springer, 1998)
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Iterative numerical methods are an important ingredient for the solution of continuous time Markov dependability models of fault-tolerant systems.
In this paper we make a numerical comparison of several splitting-based ...
On the use of error detecting and correcting codes to boost security in caches against side channel attacks
(2015)
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Microprocessor memory is sensitive to cold boot attacks. In this kind of attacks, memory remanence is exploited to download its content after the microprocessor has been struck by a hard boot. If just in this moment, a ...
Analog circuit test based on a digital signature
(2010)
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Production verification of analog circuit specifica-
tions is a challenging task requiring expensive test equipment
and time consuming procedures. This paper presents a method
for low cost on-chip parameter verification ...
Validation of aproximate dependability models of a RAID architecture with orthogonal organization
(2003)
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RAID (Redundant Array of Inexpensive Disks) are widely used in storage servers. Level-5 RAID is one of the most popular RAID architectures. Numerical analysis of exact Markovian dependability models of level-5 RAID ...
Project nº 1609: System measurement and architecture techniques (SMART)
(Kluwer Academic Publishers, 1989-12-31)
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The SMART project aims to assist the designers of real-time fault-tolerant (RT/FT) systems by providing a number of specially-developed tools within an open environment. The tools developed within the SMART environment ...
Verifying analog circuits based on a digital signature
(2009)
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Verification of analog circuit specifications is a
challenging task requiring expensive test equipment and time
consuming procedures. This paper presents a method for low
cost parameter verification based on statistical ...
Transient noise failures in SRAM cells: dynamic noise margin metric
(IEEE Computer Society Publications, 2011)
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Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and ...
Reliability estimation at block-level granularity of spin-transfer-torque MRAMs
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
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In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under ...
A low area probing detector for security IC's
(2014)
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In this paper, a low cost, Low Area Probing Detector (LAPD)
is presented. Probing or microprobing is an attack technique against integrated circuits implementing security functions, such as OTP tokens
or smartcards. It ...