Enviaments recents

  • The Mont-Blanc prototype: an alternative approach for high-performance computing systems 

    Rajovic, Nikola; Ramírez Bellido, Alejandro; Rico, Alejandro; Mantovani, Filippo; Ruiz, Daniel; Villarubi, Oriol; Gómez, Constantino; Backes, Luna; Nieto, Diego; Servat, Harald; Martorell Bofill, Xavier; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Adeniyi-Jones, Chris; Derradji, Said; Gloaguen, Hervé; Lanucara, Piero; Sanna, Nico; Mehaut, Jean-François; Pouget, Kevin; Videau, Brice; Boyer, Eric; Allalen, Momme; Auweter, Axel; Brayford, David; Tafani, Daniele; Brömmel, Dirk; Halver, René; Meinke, Jan H.; Beivide Palacio, Ramon; Benito, Mariano; Vallejo, Enrique (2016)
    Report de recerca
    Accés obert
    High-performance computing (HPC) is recognized as one of the pillars for further advance of science, industry, medicine, and education. Current HPC systems are being developed to overcome emerging challenges in order to ...
  • Exploiting asynchrony from exact forward recovery for DUE in iterative solvers 

    Jaulmes, Luc; Casas Guix, Marc; Moreto Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2015)
    Report de recerca
    Accés obert
    This paper presents a method to protect iterative solvers from Detected and Uncorrected Errors (DUE) relying on error detection techniques already available in commodity hardware. Detection operates at the memory page ...
  • Commit on overflow 

    Stipic, Srdjan; Armejach, Adrià; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2014)
    Report de recerca
    Accés obert
    Current commercial CPUs have hardware support for speculative lock elision (SLE). SLE tries to elide the lock by speculatively executing lock protected critical section. If the speculation fails, SLE acquires the lock and ...
  • Per-task energy accounting in computing systems 

    Liu, Qixiao; Jiménez, Víctor; Moreto Planas, Miquel; Abella, Jaume; Cazorla, Francisco; Valero Cortés, Mateo (2013)
    Report de recerca
    Accés obert
    We present for the first time the concept of per-task energy accounting (PTEA) and relate it to per-task energy metering (PTEM). We show the benefits of supporting both in future computing systems. Using the shared last-level ...
  • CUsched: multiprogrammed workload scheduling on GPU architectures 

    Tanasic, Ivan; Gelado Fernandez, Isaac; Cabezas, Javier; Navarro, Nacho; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2013)
    Report de recerca
    Accés obert
    Graphic Processing Units (GPUs) are currently widely used in High Performance Computing (HPC) applications to speed-up the execution of massively-parallel codes. GPUs are well-suited for such HPC environments because ...
  • Solving matrix problems with no size restriction on a systolic array processor 

    Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1986)
    Report de recerca
    Accés obert
    In this paper we propose several data structures partitioning and transformation schemes, in order to get an efficient execution of various matrix algorithms without any size resriction. The following matrix operations are ...
  • Computing size-independent matrix problems on systolic array processors 

    Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1985)
    Report de recerca
    Accés obert
    A methodology to transform dense to banded matrices is presented in this paper. This transformation, is accomplished by triangular blocks partitioning, and allows the implementation of silutions to problems with any given ...
  • Keeping control transfer instructions out of the pipeline in architectures without condition codes 

    Cortadella Fortuny, Jordi; Llaberia Griñó, José M.; González Colás, Antonio María (1987-05)
    Report de recerca
    Accés obert
    The execution of branch instructions involves a loss of performance in pipelined processors. In this paper we present a mechanism for executing this kind of instruction with a zero delay. This mechanism has been proposed ...
  • Shared queues in buffered multistage interconnection networks 

    Domingo Pascual, Jordi; Labarta Mancho, Jesús José; Casals, Olga; Llaberia Griñó, José M.; Valero Cortés, Mateo (1988-01)
    Report de recerca
    Accés obert
    This paper analyses the behaviour of a normal buffered delta network and as a result proposes the use of a shared queue instead of the two queues of the usual switching elements. The performance of the networks with ...
  • FIMSIM: A fault injection infrastructure for microarchitectural simulators 

    Yalcin, Gulay; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2011)
    Report de recerca
    Accés obert
    Fault injection is a widely used approach for experiment-based dependability evaluation in which faults can be injected to the hardware, to the simulator or to the software. Simulation based fault injection is more appealing ...

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