Enviaments recents

  • ALOJA: A framework for benchmarking and predictive analytics in Hadoop deployments 

    Berral García, Josep Lluís; Poggi Mastrokalo, Nicolas; Carrera Pérez, David; Call, Aaron; Reinauer, Rob; Green, Daron (Institute of Electrical and Electronics Engineers (IEEE), 2015-10)
    Article
    Accés obert
    This article presents the ALOJA project and its analytics tools, which leverages machine learning to interpret Big Data benchmark performance data and tuning. ALOJA is part of a long-term collaboration between BSC and ...
  • Task scheduling techniques for asymmetric multi-core systems 

    Chronaki, Kallia; Rico, Alejandro; Casas, Marc; Moreto Planas, Miquel; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2016-11-29)
    Article
    Accés obert
    As performance and energy efficiency have become the main challenges for next-generation high-performance computing, asymmetric multi-core architectures can provide solutions to tackle these issues. Parallel programming ...
  • Data stream classification using random feature functions and novel method combinations 

    Marrón Vida, Diego; Read, Jesse; Bifet, Albert; Navarro Mas, Nacho (2017-05-01)
    Article
    Accés restringit per política de l'editorial
    Big Data streams are being generated in a faster, bigger, and more commonplace. In this scenario, Hoeffding Trees are an established method for classification. Several extensions exist, including high performing ensemble ...
  • Instruction fetch architectures and code layout optimizations 

    Ramírez Bellido, Alejandro; Larriba Pey, Josep; Valero Cortés, Mateo (2001-11)
    Article
    Accés obert
    The design of higher performance processors has been following two major trends: increasing the pipeline depth to allow faster clock rates, and widening the pipeline to allow parallel execution of more instructions. Designing ...
  • Initial results on fuzzy floating point computation for multimedia processors 

    Álvarez Martínez, Carlos; Corbal San Adrián, Jesús; Salamí San Juan, Esther; Valero Cortés, Mateo (2002-01)
    Article
    Accés obert
    During the recent years, the market of mid/low-end portable systems such as PDAs or mobile digital phones have experimented a revolution in both selling volume and features as handheld devices incorporate Multimedia ...
  • Exploiting instruction-and data-level parallelism 

    Espasa Sans, Roger; Valero Cortés, Mateo (1997-09)
    Article
    Accés obert
    Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to ...
  • A case for resource-conscious out-of-order processors 

    Cristal Kestelman, Adrián; Martínez, José F; Llosa Espuny, José Francisco; Valero Cortés, Mateo (2003-12)
    Article
    Accés obert
    Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files ...
  • Software trace cache 

    Ramírez Bellido, Alejandro; Larriba Pey, Josep; Valero Cortés, Mateo (2005-01)
    Article
    Accés obert
    We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details ...
  • Kilo-instruction processors: overcoming the memory wall 

    Cristal Kestelman, Adrián; Santana Jaria, Oliverio J.; Cazorla, Francisco; Galluzzi, Marco; Ramirez Garcia, Tanausú; Pericas, Miquel; Valero Cortés, Mateo (2005-05)
    Article
    Accés obert
    Historically, advances in integrated circuit technology have driven improvements in processor microarchitecture and led to todays microprocessors with sophisticated pipelines operating at very high clock frequencies. ...
  • MInGLE: An efficient framework for domain acceleration using low-power specialized functional units 

    González Álvarez, Cecilia Noemí; Sartor, Jennifer B.; Álvarez Martínez, Carlos; Jiménez González, Daniel; Eeckhout, Lieven (2016-06)
    Article
    Accés obert
    The end of Dennard scaling leads to new research directions that try to cope with the utilization wall in modern chips, such as the design of specialized architectures. Processor customization utilizes transistors more ...

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