Enviaments recents

  • A case for resource-conscious out-of-order processors 

    Cristal Kestelman, Adrián; Martínez, José F; Llosa Espuny, José Francisco; Valero Cortés, Mateo (2003-12)
    Article
    Accés obert
    Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files ...
  • Software trace cache 

    Ramírez Bellido, Alejandro; Larriba Pey, Josep; Valero Cortés, Mateo (2005-01)
    Article
    Accés obert
    We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details ...
  • Kilo-instruction processors: overcoming the memory wall 

    Cristal Kestelman, Adrián; Santana Jaria, Oliverio J.; Cazorla, Francisco; Galluzzi, Marco; Ramirez Garcia, Tanausú; Pericas, Miquel; Valero Cortés, Mateo (2005-05)
    Article
    Accés obert
    Historically, advances in integrated circuit technology have driven improvements in processor microarchitecture and led to todays microprocessors with sophisticated pipelines operating at very high clock frequencies. ...
  • MInGLE: An efficient framework for domain acceleration using low-power specialized functional units 

    González Álvarez, Cecilia Noemí; Sartor, Jennifer B.; Álvarez Martínez, Carlos; Jiménez González, Daniel; Eeckhout, Lieven (2016-06)
    Article
    Accés obert
    The end of Dennard scaling leads to new research directions that try to cope with the utilization wall in modern chips, such as the design of specialized architectures. Processor customization utilizes transistors more ...
  • Main memory in HPC: do we need more, or could we live with less? 

    Zivanovic, Darko; Pavlovic, Milan; Radulovic, Milan; Shin, Hyunsung; Son, Jongpil; McKee, Sally A.; Carpenter, Paul M.; Radojkovic, Petar; Ayguadé Parra, Eduard (2017-03)
    Article
    Accés obert
    An important aspect of High-Performance Computing (HPC) system design is the choice of main memory capacity. This choice becomes increasingly important now that 3D-stacked memories are entering the market. Compared with ...
  • BIGNASim: a NoSQL database structure and analysis portal for nucleic acids simulation data 

    Hospital, Adam; Andrio, Pau; Cugnasco, Cesare; Codo, Laia; Becerra Fontal, Yolanda; Dans, Pablo D.; Battistini, Federica; Torres Viñals, Jordi; Goñi, Ramon; Orozco, Modesto; Gelpi, Josep Lluis (2016-01-04)
    Article
    Accés obert
    Molecular dynamics simulation (MD) is, just behind genomics, the bioinformatics tool that generates the largest amounts of data, and that is using the largest amount of CPU time in supercomputing centres. MD trajectories ...
  • Fuzzy memoization for floating-point multimedia applications 

    Álvarez Martínez, Carlos; Corbal San Adrián, Jesús; Valero Cortés, Mateo (2005-07)
    Article
    Accés obert
    Instruction memoization is a promising technique to reduce the power consumption and increase the performance of future low-end/mobile multimedia systems. Power and performance efficiency can be improved by reusing instances ...
  • Explaining dynamic cache partitioning speed ups 

    Moreto Planas, Miquel; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-01)
    Article
    Accés obert
    Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, ...
  • Coarse grain parallelization of deep neural networks 

    González Tallada, Marc (2016-08-01)
    Article
    Accés restringit per política de l'editorial
    Deep neural networks (DNN) have recently achieved extraordinary results in domains like computer vision and speech recognition. An essential element for this success has been the introduction of high performance computing ...
  • Enlarging instruction streams 

    Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-10)
    Article
    Accés obert
    The stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially ...

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