Reports de recerca: Enviaments recents

Ara es mostren els items 1-12 de 13

    • Boosting point cloud search with a vector unit 

      Exenberger Becker, Pedro Henrique; Arnau Montañés, José María; González Colás, Antonio María (2023)
      Report de recerca
      Accés obert
      Modern robots collect and process point clouds to perform accurate registration and segmentation. The most time-consuming kernel within point cloud processing -namely neighbor search- relies on appropriate data structures, ...

    • Analyzing and improving hardware modeling of Accel-Sim 

      Huerta Gañán, Rodrigo; Abaie Shoushtary, Mojtaba; González Colás, Antonio María (2023-10)
      Report de recerca
      Accés obert
      GPU architectures have become popular for executing generalpurpose programs. Their many-core architecture supports a large number of threads that run concurrently to hide the latency among dependent instructions. In modern ...

    • Keeping control transfer instructions out of the pipeline in architectures without condition codes 

      Cortadella, Jordi; Llaberia Griñó, José M.; González Colás, Antonio María (1987-05)
      Report de recerca
      Accés obert
      The execution of branch instructions involves a loss of performance in pipelined processors. In this paper we present a mechanism for executing this kind of instruction with a zero delay. This mechanism has been proposed ...

    • Una herramienta automática de feedback para ensamblador 

      Álvarez Martínez, Carlos; Jiménez González, Daniel; López Álvarez, David; Alonso López, Javier; Tous Liesa, Rubén; Parcerisa Bundó, Joan Manuel; Barlet Ros, Pere; Fernández Barta, Montserrat; Tubella Murgadas, Jordi; Pérez, Christian (2008-10)
      Report de recerca
      Accés obert
      Un estudiante de primer curso de Ingeniería en Informática debe adquirir la capacidad de analizar y depurar códigos, tanto a alto nivel como en ensamblador. Este proceso requiere una participación activa por parte de los ...

    • Process variability in sub-16nm bulk CMOS technology 

      Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon (2012-03-01)
      Report de recerca
      Accés obert
      The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.

    • Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-04-15)
      Report de recerca
      Accés obert
      In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations.

    • A selective logging mechanism for hardware transactional memory systems 

      Lupon Navazo, Marc; Magklis, Grigorios; González Colás, Antonio María (2011-09-19)
      Report de recerca
      Accés obert
      Log-based Hardware Transactional Memory (HTM) systems offer an elegant solution to handle speculative data that overflow transactional L1 caches. By keeping the pre-transactional values on a software-resident log, speculative ...

    • On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-12-05)
      Report de recerca
      Accés restringit per política de l'editorial
      In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive ...

    • Implementing a hybrid SRAM / eDRAM NUCA architecture 

      Lira Rueda, Javier; Molina Clemente, Carlos; Brooks, David; González Colás, Antonio María (2010-08-27)
      Report de recerca
      Accés obert
      In this paper, we propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. We demonstrate, that due to the high locality found in emerging ...

    • vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2010-09-05)
      Report de recerca
      Accés obert
      In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is ...

    • FOCSI: A new layout regularity metric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
      Report de recerca
      Accés obert
      Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ...

    • Last Bank: dealing with address reuse in non-uniform cache architecture for CMPs 

      Lira Rueda, Javier; Molina Clemente, Carlos; González Colás, Antonio María (2009-01-16)
      Report de recerca
      Accés obert
      In response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latencies. This architecture divides a large memory ...