Recent Submissions

  • Una herramienta automática de feedback para ensamblador 

    Álvarez Martínez, Carlos; Jiménez González, Daniel; López Álvarez, David; Alonso López, Javier; Tous Liesa, Rubén; Parcerisa Bundó, Joan Manuel; Barlet Ros, Pere; Fernández Barta, Montserrat; Tubella Murgadas, Jordi; Pérez, Christian (2008-10)
    External research report
    Open Access
    Un estudiante de primer curso de Ingeniería en Informática debe adquirir la capacidad de analizar y depurar códigos, tanto a alto nivel como en ensamblador. Este proceso requiere una participación activa por parte de los ...
  • Process variability in sub-16nm bulk CMOS technology 

    Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon (2012-03-01)
    External research report
    Open Access
    The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.
  • Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-04-15)
    External research report
    Open Access
    In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations.
  • A selective logging mechanism for hardware transactional memory systems 

    Lupon Navazo, Marc; Magklis, Grigorios; González Colás, Antonio María (2011-09-19)
    External research report
    Open Access
    Log-based Hardware Transactional Memory (HTM) systems offer an elegant solution to handle speculative data that overflow transactional L1 caches. By keeping the pre-transactional values on a software-resident log, speculative ...
  • On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-12-05)
    External research report
    Restricted access - publisher's policy
    In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive ...
  • Implementing a hybrid SRAM / eDRAM NUCA architecture 

    Lira Rueda, Javier; Molina Clemente, Carlos; Brooks, David; González Colás, Antonio María (2010-08-27)
    External research report
    Open Access
    In this paper, we propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. We demonstrate, that due to the high locality found in emerging ...
  • vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2010-09-05)
    External research report
    Open Access
    In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is ...
  • FOCSI: A new layout regularity metric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
    External research report
    Open Access
    Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ...
  • Last Bank: dealing with address reuse in non-uniform cache architecture for CMPs 

    Lira Rueda, Javier; Molina Clemente, Carlos; González Colás, Antonio María (2009-01-16)
    External research report
    Open Access
    In response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latencies. This architecture divides a large memory ...
  • LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors 

    Lira Rueda, Javier; Molina Clemente, Carlos; González Colás, Antonio María (2009-05-14)
    External research report
    Open Access
    The increasing speed-gap between processor and memory and the limited memory bandwidth make last-level cache performance crucial for CMP architectures. Non Uniform Cache Architectures (NUCA) has been introduced to deal ...

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