Enviaments recents

  • Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation 

    Rana, Manish; Canal Corretger, Ramon; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2017-03-01)
    Article
    Accés obert
    Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ...
  • Executing algorithms with hypercube topology on torus multicomputers 

    González Colás, Antonio María; Valero García, Miguel; Díaz de Cerio Ripalda, Luis Manuel (1995-08)
    Article
    Accés obert
    Many parallel algorithms use hypercubes as the communication topology among their processes. When such algorithms are executed on hypercube multicomputers the communication cost is kept minimum since processes can be ...
  • Exploiting narrow values for soft error tolerance 

    Ergin, Oguz; Unsal, Osman Sabri; Vera Rivera, Francisco Javier; González Colás, Antonio María (2006-07)
    Article
    Accés obert
    Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. ...
  • Reliability: fallacy or reality? 

    González Colás, Antonio María; Mahlke, Scott; Mukherjee, Shubu; Sendag, Resit; Chiou, Derek; Yi, Joshua J. (2007-11)
    Article
    Accés obert
    As chip architects and manufacturers plumb ever-smaller process technologies, new species of faults are compromising device reliability, following an introduction by the authors debate whether reliability is a legitimate ...
  • Thread partitioning and value prediction for exploiting speculative thread-level parallelism 

    Marcuello, Pedro; González Colás, Antonio María; Tubella Murgadas, Jordi (2004-02)
    Article
    Accés obert
    Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model ...
  • Understanding the thermal implications of multicore architectures 

    Chaparro, Pedro; González González, José; Magklis, Grigorios; Cai, Qiong; González Colás, Antonio María (2007-08)
    Article
    Accés obert
    Multicore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations ...
  • Reducing branch delay to zero in pipelined processors 

    González Colás, Antonio María; Llaberia Griñó, José M. (1993-03)
    Article
    Accés obert
    A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution ...
  • Randomized cache placement for eliminating conflicts 

    Topham, Nigel; González Colás, Antonio María (1999-02)
    Article
    Accés obert
    Applications with regular patterns of memory access can experience high levels of cache conflict misses. In shared-memory multiprocessors conflict misses can be increased significantly by the data transpositions required ...
  • Refueling: Preventing wire degradation due to electromigration 

    Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Unsal, Osman Sabri; Ergin, Oguz; González Colás, Antonio María; Tschanz, James W. (2008-12)
    Article
    Accés obert
    Electromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable wires. Refueling exploits EM's self-healing effect by balancing ...
  • Control speculation for energy-efficient next-generation superscalar processors 

    Aragón, Juan Luis; González González, José; González Colás, Antonio María (2006-03)
    Article
    Accés obert
    Conventional front-end designs attempt to maximize the number of "in-flight" instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, ...

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