Enviaments recents

  • Leveraging register windows to reduce physical registers to the bare minimum 

    Quiñones Moreno, Eduardo; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2010-12)
    Article
    Accés obert
    Register window is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register requirements ...
  • Late allocation and early release of physical registers 

    Monreal Arnal, Teresa; Viñals Yufera, Víctor; González González, José; González Colás, Antonio María; Valero Cortés, Mateo (2004-10)
    Article
    Accés obert
    The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the ...
  • Parsar: parallelisation of a chirp scaling algorithm sar processor 

    MARTINEZ, A; Fraile, F; Mallorquí Franquet, Jordi Joan; Nogueira, J; Gabalda, J; Broquetas Ibars, Antoni; González Colás, Antonio María (1997-08)
    Article
    Accés restringit per política de l'editorial
    A parallel SAR processor is presented in this paper. The target configuration is a cluster of UNIX workstations, available in most user sites. This fact allows to obtain an increased computing performance without the need ...
  • Scalability of broadcast performance in wireless network-on-chip 

    Abadal Cavallé, Sergi; Mestres Sugrañes, Albert; Nemirovsky, Mario; Lee, Heekwan; González Colás, Antonio María; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2016-12-01)
    Article
    Accés obert
    Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors ...
  • Shared resource aware scheduling on power-constrained tiled many-core processors 

    Jha, Sudhanshu Shekhar; Heirman, Wim; Falcón Samper, Ayose Jesus; Tubella Murgadas, Jordi; González Colás, Antonio María; Eeckhout, Lieven (2017-02-01)
    Article
    Accés restringit per política de l'editorial
    Power management through dynamic core, cache and frequency adaptation is becoming a necessity in today’s power-constrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation ...
  • Impact of parameter variations on circuits and microarchitecture 

    Unsal, Osman Sabri; Tschanz, James W.; Bowman, Keith; De, Vivek; Vera Rivera, Francisco Javier; González Colás, Antonio María; Ergin, Oguz (2006-12)
    Article
    Accés obert
    Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace ...
  • Improving latency tolerance of multithreading through decoupling 

    Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2001-10)
    Article
    Accés obert
    The increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, ...
  • Hypercube algorithms on mesh connected multicomputers 

    Díaz de Cerio Ripalda, Luis Manuel; Valero García, Miguel; González Colás, Antonio María (2002-12)
    Article
    Accés obert
    A new methodology named CALMANT (CC-cube Algorithms on Meshes and Tori) for mapping a type of algorithm that we call CC-cube algorithm onto multicomputers with hypercube, mesh, or torus interconnection topology is proposed. ...
  • AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures 

    Aleta Ortega, Alexandre; Codina Viñas, Josep M.; Sánchez Navarro, F. Jesús; González Colás, Antonio María; Kaeli, D (2009-06)
    Article
    Accés obert
    This paper presents AGAMOS, a technique to modulo schedule loops on clustered microarchitectures. The proposed scheme uses a multilevel graph partitioning strategy to distribute the workload among clusters and reduces the ...
  • An energy-efficient memory unit for clustered microarchitectures 

    Bieschewski, Stefan; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2016-08-01)
    Article
    Accés obert
    Whereas clustered microarchitectures themselves have been extensively studied, the memory units for these clustered microarchitectures have received relatively little attention. This article discusses some of the inherent ...

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