Data placement in HPC architectures with heterogeneous off-chip memory
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés restringit per política de l'editorial (embargat fins 2017-12-01)
The performance of HPC applications is often bounded by the underlying memory system's performance. The trend of increasing the number of cores on a chip imposes even higher memory bandwidth and capacity requirements. The limitations of traditional memory technologies are pushing research in the direction of hybrid memory systems that, besides DRAM, include one or more modules based on some of the higher-density non-volatile memory technologies, where one of them will provide the required bandwidth, while the other will provide the required capacity for the application. This creates many challenges with data placement and migration policies between the modules of such hybrid memory system. In this paper, we propose an architecture with a hybrid memory design that places two technologically different memory modules in a flat address space. On such system, we evaluate several HPC workloads against different data placement and migration policies, compare their performance by means of execution time and the number of non-volatile memory writes, and consider how it can be applied to the future HPC architectures. Our results show that the hybrid memory system with dynamic page migration and limited DRAM capacity, can achieve performance that is comparable to a hypothetical, hard to implement, DRAM-only system.
CitacióPavlovic, M.; Puzovic, N.; Alex Ramirez. Data placement in HPC architectures with heterogeneous off-chip memory. A: IEEE International Conference on Computer Design. "2013 IEEE 31st International Conference on Computer Design (ICCD): October 6-9, 2013, Asheville, NC, USA". Asheville, NC: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 193-200.