VPPET: virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms
Tipo de documentoTexto en actas de congreso
Fecha de publicación2014
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condiciones de accesoAcceso restringido por política de la editorial
Using low-power symmetric multi-cores on FPGAs are becoming ubiquitous in embedded computing. This is due to the emergence of power and energy as key design metrics, as important as performance. This leads to the requirement of powerful and reliable tools, which will be used for the Design Space Exploration (DSE) based on power and energy at an early stage of the design flow. In this paper, we propose a simulation based virtual platform power and energy estimation tool for heterogeneous Multiprocessor System-on-Chip (MPSoC) based platforms. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for different parts of the system. This is a one-time activity. In the second step, a simulation based virtual platform framework is developed to accurately grab the activities used in the related power models generated in the first step. The combination of the two steps leads to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool is automated and also scalable for exploring complex embedded multi-core architectures. The efficiency of the proposed tool is validated through multi-cores/processors designed around the FPGAs and extended to accommodate futuristic multi-processors/cores for a reliable energy based DSE. The obtained power/energy estimation results provide less than 4% of error for single core processor, 8% for dual-core processor and 9% for heterogeneous MPSoC based systems when compared to real board measurements.
CitaciónRethinagiri, S. [et al.]. VPPET: virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms. A: International Workshop on Power and Timing Modeling, Optimization and Simulation. "14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2014): Palma de Mallorca, Spain: 29 September-1 October 2014". Palma de Mallorca: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 6951910-1-6951910-8.
Versión del editorhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6951910
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