A crosstalk latch circuit design
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range of or even higher than ±Vdd, becoming under specific conditions a dynamic latch preserving the system from the propagation of unknown quality information. The circuit and the design rules presented are oriented to VLSI circuits design in which crosstalk perturbations may be foreseen
CitationRubio, A.; Pons, J.; Anglada, R. A crosstalk latch circuit design. A: IEEE International Midwest Symposium on Circuits and Systems. "33rd Midwest Symposium on Circuits and Systems: Calgary Convention Centre: Calgary, Alberta, Canada: August 12-15, 1990". Calgary: Institute of Electrical and Electronics Engineers (IEEE), 1990, p. 653-656.
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