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Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
dc.contributor.author | Gómez Fernández, Sergio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.author | Mauricio Ferré, Juan |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2015-03-18T11:37:15Z |
dc.date.available | 2015-03-18T11:37:15Z |
dc.date.created | 2014-07-01 |
dc.date.issued | 2014-07-01 |
dc.identifier.citation | Gomez, S.; Moll, F.; Mauricio, J. Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations. "Journal of micro/nanolithography, MEMS and MOEMS", 01 Juliol 2014, vol. 13, núm. 3. |
dc.identifier.issn | 1932-5150 |
dc.identifier.uri | http://hdl.handle.net/2117/26792 |
dc.description.abstract | A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE) |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Nanoelectronics |
dc.subject.lcsh | Lithography |
dc.subject.other | Design for manufacturability |
dc.subject.other | Lithography hotspots |
dc.subject.other | Yield estimation |
dc.subject.other | Layout design |
dc.title | Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations |
dc.type | Article |
dc.subject.lemac | Nanoelectrònica |
dc.subject.lemac | Litografia |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1117/1.JMM.13.3.033016 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://nanolithography.spiedigitallibrary.org/article.aspx?articleid=1906672 |
dc.rights.access | Open Access |
local.identifier.drac | 15270703 |
dc.description.version | Postprint (author’s final draft) |
local.citation.author | Gomez, S.; Moll, F.; Mauricio, J. |
local.citation.publicationName | Journal of micro/nanolithography, MEMS and MOEMS |
local.citation.volume | 13 |
local.citation.number | 3 |
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