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Design and implementation of automatic test equipment IP module
| dc.contributor.author | Fransi Palos, Sergi |
| dc.contributor.author | Farre Lozano, Goretti |
| dc.contributor.author | Garcia Deiros, Lucas |
| dc.contributor.author | Manich Bou, Salvador |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
| dc.date.accessioned | 2015-03-18T08:50:30Z |
| dc.date.created | 2010-05-24 |
| dc.date.issued | 2010-05-24 |
| dc.identifier.citation | Fransi, S. [et al.]. Design and implementation of automatic test equipment IP module. A: IEEE European Test Symposium. "15th IEEE European Test Symposium: 24-28 May 2010: ETS 2010, Praga : digest of papers". Praga: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 244. |
| dc.identifier.isbn | 978-1-4244-5833-2 |
| dc.identifier.uri | http://hdl.handle.net/2117/26780 |
| dc.description.abstract | This paper presents an Intellectual Property (IP) module that includes fully functional autonomous Automatic Test Equipment (ATE). The module analyses responses from the Device Under Test (DUT) after sending test vectors to the device. Communication with the DUT is maintained through a synchronous bidirectional serial channel. The module has been designed for a fail-safe level of security, which means any single fault producing an erroneous output is detected. Several IP-ATEs can be synthesized in a single hardware platform to operate independently or coordinately. |
| dc.format.extent | 1 p. |
| dc.language.iso | eng |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
| dc.subject.lcsh | Digital integrated circuits -- Testing |
| dc.subject.other | Automatic Testing |
| dc.subject.other | Digital Circuits |
| dc.subject.other | Field Programmable Gate Arrays |
| dc.subject.other | Intellectual Property |
| dc.subject.other | Low Power Tester |
| dc.subject.other | Low Cost ICs |
| dc.subject.other | Multisite Tester. |
| dc.title | Design and implementation of automatic test equipment IP module |
| dc.type | Conference lecture |
| dc.subject.lemac | Circuits integrats digitals -- Proves |
| dc.contributor.group | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
| dc.identifier.dl | CFP10216-USB |
| dc.rights.access | Restricted access - publisher's policy |
| local.identifier.drac | 2543199 |
| dc.description.version | Postprint (published version) |
| dc.date.lift | 10000-01-01 |
| local.citation.author | Fransi, S.; Farre, G.; Deiros, L. G.; Manich, S. |
| local.citation.contributor | IEEE European Test Symposium |
| local.citation.pubplace | Praga |
| local.citation.publicationName | 15th IEEE European Test Symposium: 24-28 May 2010: ETS 2010, Praga : digest of papers |
| local.citation.startingPage | 244 |
| local.citation.endingPage | 244 |