Advanced pattern based memory controller for FPGA based HPC applications
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés restringit per política de l'editorial
Projecte de la Comissió EuropeaRiding on Moore's Law (EC-FP7-321253)
The ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which supports both regular and irregular memory patterns. The proposed memory controller systematically reduces the latency faced by processors/accelerators due to irregular memory access patterns and low memory bandwidth by using a smart mechanism that collects and stores the different patterns and reuses them when it is needed. In order to prove the effectiveness of the proposed controller, we implemented and tested it on a Xilinx ML505 FPGA board. In order to prove that our controller is efficient in a variety of scenarios, we used several benchmarks with different memory access patterns. The benchmarking results show that our controller consumes 20% less hardware resources, 32% less on chip power and achieves a maximum speedup of 52× and 2.9× for regular and irregular applications respectively.
CitacióHussain, T. [et al.]. Advanced pattern based memory controller for FPGA based HPC applications. A: International Conference on High Performance Computing & Simulation. "Proceedings of the 2014 International Conference on High Performance Computing and Simulation: July 21-25, 2014, Bologna, Italy". Bologna: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 287-294.
Versió de l'editorhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6903697
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