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PVMC: Programmable Vector Memory Controller
dc.contributor.author | Hussain, Tassadaq |
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2014-11-11T13:38:03Z |
dc.date.created | 2014 |
dc.date.issued | 2014 |
dc.identifier.citation | Hussain, T. [et al.]. PVMC: Programmable Vector Memory Controller. A: International Conference on Application-Specific Systems, Architectures and Processors. "2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors: (ASAP 2014): 18-20 June 2014: Zurich, Switzerland". Zurich: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 240-247. |
dc.identifier.isbn | 978-1-4799-3608-3 |
dc.identifier.uri | http://hdl.handle.net/2117/24680 |
dc.description.abstract | In this work, we propose a Programmable Vector Memory Controller (PVMC), which boosts noncontiguous vector data accesses by integrating descriptors of memory patterns, a specialized local memory, a memory manager in hardware, and multiple DRAM controllers. We implemented and validated the proposed system on an Altera DE4 FPGA board. We compare the performance of our proposal with a vector system without PVMC as well as a scalar only system. When compared with a baseline vector system, the results show that the PVMC system transfers data sets up to 2.2× to 14.9× faster, achieves between 2.16× to 3.18× of speedup for 5 applications and consumes 2.56 to 4.04 times less energy. © 2014 IEEE. |
dc.description.sponsorship | The research leading to these results has received funding from the European Research Council under the European Unions 7th FP (FP/2007-2013) / ERC GA n. 321253. It has been partially funded by the Spanish Government (TIN2012-34557). |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures distribuïdes |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació |
dc.subject.lcsh | Random access memory |
dc.subject.lcsh | Memory management (Computer science) |
dc.subject.other | Computer architecture |
dc.subject.other | Controllers |
dc.subject.other | Dynamic random access storage |
dc.subject.other | Baseline vectors |
dc.subject.other | FPGA boards |
dc.subject.other | Local memory |
dc.subject.other | Memory controller |
dc.subject.other | Memory manager |
dc.subject.other | Memory patterns |
dc.subject.other | Vector data |
dc.subject.other | Vector systems |
dc.subject.other | Vectors |
dc.title | PVMC: Programmable Vector Memory Controller |
dc.type | Conference report |
dc.subject.lemac | Gestió de memòria (Informàtica) |
dc.subject.lemac | Ordinadors -- Dispositius de memòria |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/ASAP.2014.6868668 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6868668 |
dc.rights.access | Open Access |
local.identifier.drac | 15225911 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
dc.date.lift | 10000-01-01 |
local.citation.author | Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M. |
local.citation.contributor | International Conference on Application-Specific Systems, Architectures and Processors |
local.citation.pubplace | Zurich |
local.citation.publicationName | 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors: (ASAP 2014): 18-20 June 2014: Zurich, Switzerland |
local.citation.startingPage | 240 |
local.citation.endingPage | 247 |