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An accurate and Verilog-A compatible compact model for graphene field-effect transistors
dc.contributor.author | Landauer, Gerhard Martin |
dc.contributor.author | González Jiménez, José Luis |
dc.contributor.author | Jiménez Jiménez, David |
dc.date.accessioned | 2014-10-17T08:29:10Z |
dc.date.created | 2014-06-04 |
dc.date.issued | 2014-06-04 |
dc.identifier.citation | Landauer, G.M.; González, J.L.; Jiménez, D. An accurate and Verilog-A compatible compact model for graphene field-effect transistors. "IEEE transactions on nanotechnology", 04 Juny 2014, vol. 13, núm. 5, p. 895-904. |
dc.identifier.issn | 1536-125X |
dc.identifier.uri | http://hdl.handle.net/2117/24401 |
dc.description.abstract | The present paper provides an accurate drift-diffusion model of the graphene field-effect transistor (GFET). A precise yet mathematically simple current-voltage relation is derived by focusing on device physics at energy levels close to the Dirac point. With respect to previous work, our approach extends modeling accuracy to the low-voltage biasing regime and improves the prediction of current saturation. These advantages are highlighted by a comparison study of the drain current, transconductance, output conductance, and intrinsic gain. The model has been implemented in Verilog-A and is compatible with conventional circuit simulators. It is provided as a tool for the exploration of GFET-based integrated circuit design. The model shows good agreement with measurement data from GFET prototypes. |
dc.format.extent | 10 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
dc.subject.lcsh | Nanotechnology |
dc.subject.other | Dirac point |
dc.subject.other | GFET-based integrated circuit design |
dc.subject.other | Verilog-A compatible compact model |
dc.subject.other | circuit simulators |
dc.subject.other | current saturation |
dc.subject.other | current-voltage relation |
dc.subject.other | drain current |
dc.subject.other | drift-diffusion model |
dc.subject.other | energy levels |
dc.subject.other | graphene field-effect transistor |
dc.subject.other | intrinsic gain |
dc.subject.other | low-voltage biasing regime |
dc.subject.other | output conductance |
dc.subject.other | transconductance |
dc.title | An accurate and Verilog-A compatible compact model for graphene field-effect transistors |
dc.type | Article |
dc.subject.lemac | Nanotecnologia |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/TNANO.2014.2328782 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6825842 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 15250511 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Landauer, G.M.; González, J.L.; Jiménez, D. |
local.citation.publicationName | IEEE transactions on nanotechnology |
local.citation.volume | 13 |
local.citation.number | 5 |
local.citation.startingPage | 895 |
local.citation.endingPage | 904 |
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