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Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
dc.contributor.author | Ganapathy, Shrikanth |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2014-09-10T07:36:08Z |
dc.date.created | 2010 |
dc.date.issued | 2010 |
dc.identifier.citation | Ganapathy, S. [et al.]. Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. A: Design, Automation and Test in Europe. "Design, Automation & Test in Europe: Dresden, Germany, March 8-12, 2010: proceedings". Dresden: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 417-422. |
dc.identifier.isbn | 978-3-9810801-6-2 |
dc.identifier.uri | http://hdl.handle.net/2117/24023 |
dc.description.abstract | With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit performance are likely to suffer the most from this phenomena. While Statistical static timing analysis (SSTA) is used extensively for this purpose, it does not account for dynamic conditions during operation. In this paper, we present a multivariate regression based technique that computes the propagation delay of circuits subject to manufacturing process variations in the presence of temporal variations like temperature. It can be used to predict the dynamic behavior of circuits under changing operating conditions. The median error between the proposed model and circuit-level simulations is below 5%. With this model, we ran a study of the effect of temperature on access time delays for 500 cache samples. The study was run in 0.557 seconds, compared to the 20h and 4min of the SPICE simulation achieving a speedup of over 1??105. As a case study, we show that the access times of caches can vary as much as 2.03?? at high temperatures in future technologies under process variations. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Integrated circuits -- Design and construction |
dc.subject.other | Cache storage |
dc.subject.other | Delays |
dc.subject.other | Integrated circuit modelling |
dc.subject.other | Regression analysis |
dc.subject.other | Timing |
dc.title | Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability |
dc.type | Conference report |
dc.subject.lemac | Circuits integrats -- Disseny i construcció |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/DATE.2010.5457167 |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 4435294 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Ganapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A. |
local.citation.contributor | Design, Automation and Test in Europe |
local.citation.pubplace | Dresden |
local.citation.publicationName | Design, Automation & Test in Europe: Dresden, Germany, March 8-12, 2010: proceedings |
local.citation.startingPage | 417 |
local.citation.endingPage | 422 |