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DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy
dc.contributor.author | Jaksic, Zoran |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2014-06-11T16:42:31Z |
dc.date.created | 2014 |
dc.date.issued | 2014 |
dc.identifier.citation | Jaksic, Z.; Canal, R. DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014". Dreden: European Interactive Digital Advertising Alliance (EDAA), 2014. |
dc.identifier.isbn | 978-398153702-4 |
dc.identifier.uri | http://hdl.handle.net/2117/23202 |
dc.description.abstract | Recent technology trends has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these cells is that they lose their state (i.e. value) over time, and they have to be refreshed. This paper proposes the implementation of coherent caches with DRAM cells. Furthermore, we propose to use the coherence state to tune the refresh overhead. According to our analysis, an average of up to 57% of refresh energy can be saved. Also, comparing to the caches implemented in SRAMs total energy savings are on average up to 39% depending of the refresh policy with a performance loss below 8%. |
dc.language.iso | eng |
dc.publisher | European Interactive Digital Advertising Alliance (EDAA) |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors::Protocols de comunicació |
dc.subject | Àrees temàtiques de la UPC::Informàtica |
dc.subject.lcsh | Memory management (Computer science) |
dc.subject.lcsh | Energy conservation |
dc.subject.other | 3T DRAM |
dc.subject.other | 6T SRAM |
dc.subject.other | cache coherence |
dc.subject.other | FinFETs |
dc.subject.other | retention time |
dc.title | DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy |
dc.type | Conference report |
dc.subject.lemac | Gestió de memòria (Informàtica) |
dc.subject.lemac | Energia -- Estalvi |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.7873/DATE2014.094 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://dl.acm.org/citation.cfm?id=2616706 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 14920667 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Jaksic, Z.; Canal, R. |
local.citation.contributor | Design, Automation and Test in Europe |
local.citation.pubplace | Dreden |
local.citation.publicationName | Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014 |