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Design-oriented analysis of quantization-induced limit cycles in a multiple-sampled digitally controlled buck converter
dc.contributor.author | Bradley, Mark |
dc.contributor.author | Alarcón Cot, Eduardo José |
dc.contributor.author | Feely, Orla |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2014-05-07T13:45:02Z |
dc.date.created | 2014-04-01 |
dc.date.issued | 2014-04-01 |
dc.identifier.citation | Bradley, M.; Alarcon, E.; Feely, O. Design-oriented analysis of quantization-induced limit cycles in a multiple-sampled digitally controlled buck converter. "IEEE transactions on circuits and systems I: regular papers", 01 Abril 2014, vol. 61, núm. 4, p. 1192-1205. |
dc.identifier.issn | 1549-8328 |
dc.identifier.uri | http://hdl.handle.net/2117/22888 |
dc.description.abstract | Digital control of switching power converters is an area which has seen increased attention in recent years. However, quantization in the feedback loop from the analog-to-digital (A/D) converter and the digital pulse width modulator (DPWM) may cause limit cycle oscillations to manifest, which are generally seen as being undesirable. This paper presents an analysis of the limit cycle behavior found in a multiple-sampled digitally controlled buck converter. The limit cycles which may arise in the system are characterized and conditions to prevent these oscillations from occurring are presented. © 2004-2012 IEEE. |
dc.format.extent | 14 p. |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència |
dc.subject.lcsh | Digital control system |
dc.subject.lcsh | Voltage-controlled oscillators |
dc.subject.other | DC-DC power converters |
dc.subject.other | Digital control |
dc.subject.other | Limit cycles |
dc.subject.other | Nonlinear dynamics |
dc.subject.other | Quantization |
dc.title | Design-oriented analysis of quantization-induced limit cycles in a multiple-sampled digitally controlled buck converter |
dc.type | Article |
dc.subject.lemac | Control digital |
dc.subject.lemac | Oscil·ladors de voltatge controlat |
dc.contributor.group | Universitat Politècnica de Catalunya. EPIC - Energy Processing and Integrated Circuits |
dc.identifier.doi | 10.1109/TCSI.2013.2283671 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6642152 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 14576791 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Bradley, M.; Alarcon, E.; Feely, O. |
local.citation.publicationName | IEEE transactions on circuits and systems I: regular papers |
local.citation.volume | 61 |
local.citation.number | 4 |
local.citation.startingPage | 1192 |
local.citation.endingPage | 1205 |
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