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Logic synthesis for manufacturability considering regularity and lithography printability
dc.contributor.author | Machado, Lucas |
dc.contributor.author | Dal Bem, Vinicius |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.author | Gómez Fernández, Sergio |
dc.contributor.author | Ribas, Renato P. |
dc.contributor.author | Reis, André Inácio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2014-04-04T17:38:26Z |
dc.date.created | 2013 |
dc.date.issued | 2013 |
dc.identifier.citation | Machado, L. [et al.]. Logic synthesis for manufacturability considering regularity and lithography printability. A: IEEE Computer Society Symposium on VLSI. "ISVLSI 2013: 2013 IEEE Computer Society Annual Symposium on VLSI: Natal, Brazil: August 5-7, 2013". Natal: IEEE Computer Society Publications, 2013, p. 230-235. |
dc.identifier.isbn | 978-1-4799-1331-2 |
dc.identifier.uri | http://hdl.handle.net/2117/22528 |
dc.description.abstract | This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, but it results in a significant area overhead by introducing regularity. To the best of our knowledge, this is the first approach that considers the tradeoff of cells with different levels of regularity and different area overheads during the logic synthesis, in order to improve overall design yield. A technology remapping tool with such yield model as cost function is proposed and implemented and interesting results are presented. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society Publications |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Integrated circuits |
dc.subject.lcsh | Lithography |
dc.subject.other | Design for manufacture |
dc.subject.other | Integrated circuit layout |
dc.subject.other | Lithography |
dc.subject.other | IC layout |
dc.subject.other | Integrated circuit manufacturing |
dc.subject.other | Lithography printability |
dc.subject.other | Logic synthesis |
dc.subject.other | technology remapping tool |
dc.subject.other | Yield loss |
dc.subject.other | Cost function |
dc.subject.other | Integrated circuit modeling |
dc.subject.other | Layout |
dc.subject.other | Libraries |
dc.subject.other | Lithography |
dc.subject.other | Semiconductor device modeling |
dc.subject.other | Superluminescent diodes |
dc.subject.other | Lithography |
dc.subject.other | Regularity |
dc.subject.other | Technology mapping |
dc.subject.other | Yield model |
dc.title | Logic synthesis for manufacturability considering regularity and lithography printability |
dc.type | Conference report |
dc.subject.lemac | Circuits integrats |
dc.subject.lemac | Litografia |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/ISVLSI.2013.6654638 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6654638&isnumber=6654605 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 12913050 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Machado, L.; Dal Bem, V.; Moll, F.; Gómez, S.; Ribas, R. P.; Reis, A. I. |
local.citation.contributor | IEEE Computer Society Symposium on VLSI |
local.citation.pubplace | Natal |
local.citation.publicationName | ISVLSI 2013: 2013 IEEE Computer Society Annual Symposium on VLSI: Natal, Brazil: August 5-7, 2013 |
local.citation.startingPage | 230 |
local.citation.endingPage | 235 |