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Study on the optimal distribution of redundancy effort in cross-layer reliable architectures
dc.contributor.author | Aymerich Capdevila, Nivard |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2014-03-20T14:42:09Z |
dc.date.created | 2013 |
dc.date.issued | 2013 |
dc.identifier.citation | Aymerich, N.; Rubio, J.A. Study on the optimal distribution of redundancy effort in cross-layer reliable architectures. A: IEEE International Conference on Nanotechnology. "Proceedings of the 13th IEEE International Conference on Nanotechnology: Beijing, China: August 5-8, 2013". Beijing: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 245-249. |
dc.identifier.isbn | 978-1-4799-0676-5 |
dc.identifier.uri | http://hdl.handle.net/2117/22318 |
dc.description.abstract | This paper presents a comprehensive approach to the smart application of redundancy techniques in multiple-layer hierarchical systems. Computing systems today are rapidly evolving into increasingly complex structures with an ever-increasing number of components. Moreover, future technology generations are expected to have associated lower levels of quality. For these reasons, it is emerging nowadays a renewed interest in the development of reliable architectures. In this work we delve into this topic putting special emphasis on the system hardware hierarchy. We analyze the advantages in terms of reliability of distributing redundancy effort in cross-layer systems. We base our analysis on a general fault model that takes into account both devices and interconnections. Using the Rent's Law we relate the number of devices and interconnections for different configurations of redundancy and compare the global error probability. Our results provide meaningful information about the benefits that can be achieved by properly choosing the system layer at which to apply redundancy, and if applicable, the optimal distribution of redundancy effort through the system layers. © 2013 IEEE. |
dc.format.extent | 5 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Nanotechnology |
dc.subject.lcsh | Fault-tolerant computing |
dc.subject.other | Analytical models |
dc.subject.other | Computer architecture |
dc.subject.other | Error probability |
dc.subject.other | Integrated circuit interconnections |
dc.subject.other | Redundancy |
dc.subject.other | Tunneling magnetoresistance |
dc.title | Study on the optimal distribution of redundancy effort in cross-layer reliable architectures |
dc.type | Conference report |
dc.subject.lemac | Nanotecnologia |
dc.subject.lemac | Tolerància als errors (Informàtica) |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/NANO.2013.6720848 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6720848 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 13666000 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Aymerich, N.; Rubio, J.A. |
local.citation.contributor | IEEE International Conference on Nanotechnology |
local.citation.pubplace | Beijing |
local.citation.publicationName | Proceedings of the 13th IEEE International Conference on Nanotechnology: Beijing, China: August 5-8, 2013 |
local.citation.startingPage | 245 |
local.citation.endingPage | 249 |