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dc.contributor.authorAymerich Capdevila, Nivard
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2014-03-20T14:42:09Z
dc.date.created2013
dc.date.issued2013
dc.identifier.citationAymerich, N.; Rubio, J.A. Study on the optimal distribution of redundancy effort in cross-layer reliable architectures. A: IEEE International Conference on Nanotechnology. "Proceedings of the 13th IEEE International Conference on Nanotechnology: Beijing, China: August 5-8, 2013". Beijing: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 245-249.
dc.identifier.isbn978-1-4799-0676-5
dc.identifier.urihttp://hdl.handle.net/2117/22318
dc.description.abstractThis paper presents a comprehensive approach to the smart application of redundancy techniques in multiple-layer hierarchical systems. Computing systems today are rapidly evolving into increasingly complex structures with an ever-increasing number of components. Moreover, future technology generations are expected to have associated lower levels of quality. For these reasons, it is emerging nowadays a renewed interest in the development of reliable architectures. In this work we delve into this topic putting special emphasis on the system hardware hierarchy. We analyze the advantages in terms of reliability of distributing redundancy effort in cross-layer systems. We base our analysis on a general fault model that takes into account both devices and interconnections. Using the Rent's Law we relate the number of devices and interconnections for different configurations of redundancy and compare the global error probability. Our results provide meaningful information about the benefits that can be achieved by properly choosing the system layer at which to apply redundancy, and if applicable, the optimal distribution of redundancy effort through the system layers. © 2013 IEEE.
dc.format.extent5 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshNanotechnology
dc.subject.lcshFault-tolerant computing
dc.subject.otherAnalytical models
dc.subject.otherComputer architecture
dc.subject.otherError probability
dc.subject.otherIntegrated circuit interconnections
dc.subject.otherRedundancy
dc.subject.otherTunneling magnetoresistance
dc.titleStudy on the optimal distribution of redundancy effort in cross-layer reliable architectures
dc.typeConference report
dc.subject.lemacNanotecnologia
dc.subject.lemacTolerància als errors (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/NANO.2013.6720848
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6720848
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac13666000
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorAymerich, N.; Rubio, J.A.
local.citation.contributorIEEE International Conference on Nanotechnology
local.citation.pubplaceBeijing
local.citation.publicationNameProceedings of the 13th IEEE International Conference on Nanotechnology: Beijing, China: August 5-8, 2013
local.citation.startingPage245
local.citation.endingPage249


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