Mostra el registre d'ítem simple
Measurements of process variability in 40-nm regular and nonregular layouts
dc.contributor.author | Mauricio Ferré, Juan |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.author | Gómez Fernández, Sergio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2014-03-14T13:31:23Z |
dc.date.created | 2014-02-01 |
dc.date.issued | 2014-02-01 |
dc.identifier.citation | Mauricio, J.; Moll, F.; Gomez, S. Measurements of process variability in 40-nm regular and nonregular layouts. "IEEE transactions on electron devices", 01 Febrer 2014, vol. 61, núm. 2, p. 365-371. |
dc.identifier.issn | 0018-9383 |
dc.identifier.uri | http://hdl.handle.net/2117/22068 |
dc.description.abstract | As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a compact and 2) nonregular layout. Experimental results show a 60% reduction in variability with a cost of 60% area overhead. |
dc.format.extent | 7 p. |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors |
dc.subject.other | Lithography distortion |
dc.subject.other | Variability |
dc.subject.other | Fluctuations |
dc.subject.other | Mosfets |
dc.title | Measurements of process variability in 40-nm regular and nonregular layouts |
dc.type | Article |
dc.subject.lemac | Circuits integrats |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/TED.2013.2294742 |
dc.description.peerreviewed | Peer Reviewed |
dc.subject.ams | Integrated circuits |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6691935 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 13607353 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/248538/EU/SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms/SYNAPTIC |
dc.date.lift | 10000-01-01 |
local.citation.author | Mauricio, J.; Moll, F.; Gomez, S. |
local.citation.publicationName | IEEE transactions on electron devices |
local.citation.volume | 61 |
local.citation.number | 2 |
local.citation.startingPage | 365 |
local.citation.endingPage | 371 |
Fitxers d'aquest items
Aquest ítem apareix a les col·leccions següents
-
Articles de revista [92]
-
Articles de revista [1.725]