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Information Leakage Reduction at the Scan-Path Output
dc.contributor.author | Manich Bou, Salvador |
dc.contributor.author | Wamser, Markus S. |
dc.contributor.author | Sigl, Georg |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2014-01-02T16:38:55Z |
dc.date.created | 2013 |
dc.date.issued | 2013 |
dc.identifier.citation | Manich, S.; S. Wamser, M.; Sigl, G. Information Leakage Reduction at the Scan-Path Output. A: Conference on Design of Circuits and Integrated Systems. "Proceedings of the XXVII Conference on Design of Circuits and Integrated Systems". Donostia - San Sebastian: 2013, p. 1-6. |
dc.identifier.isbn | 978-84-8081-401-0 |
dc.identifier.uri | http://hdl.handle.net/2117/21136 |
dc.description.abstract | In this paper we present a new scan-path structure for improving the security of systems including a scan path, which normally introduces a security critical information channel into a design. The structure, named differential scan path (DiSP), divides the internal state of the scan path into two sections. During shift-out operation, only subtraction of the two sections is provided. The discovery of the internal state from this subtraction requires guesswork that increases exponentially with scan path length. Subtraction does not preserve parity, a property sometimes used during attacks. Output subtraction cannot be reversed and hence it is not possible to restore the internal state of the chip from the output. The structure is simple, requires little area and no unlocking keys. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Integrated circuits |
dc.subject.other | security |
dc.subject.other | testability |
dc.subject.other | scan path |
dc.subject.other | attack |
dc.subject.other | smart-card |
dc.subject.other | bilbo. |
dc.title | Information Leakage Reduction at the Scan-Path Output |
dc.type | Conference report |
dc.subject.lemac | Circuits integrats -- Testeig |
dc.contributor.group | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 12934428 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Manich, S.; S. Wamser, M.; Sigl, G. |
local.citation.contributor | Conference on Design of Circuits and Integrated Systems |
local.citation.pubplace | Donostia - San Sebastian |
local.citation.publicationName | Proceedings of the XXVII Conference on Design of Circuits and Integrated Systems |
local.citation.startingPage | 1 |
local.citation.endingPage | 6 |