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dc.contributor.authorCarrasco, Juan A.
dc.contributor.authorSuñé, Víctor
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2013-12-20T09:03:38Z
dc.date.available2013-12-20T09:03:38Z
dc.date.created2004-02
dc.date.issued2004-02
dc.identifier.citationCarrasco, J.; Suñe, V. Combinatorial methods for the evaluation of yield and operational reliability of fault-tolerant systems-on-chip. "Microelectronics reliability", Febrer 2004, vol. 44, núm. 2, p. 339-350.
dc.identifier.issn0026-2714
dc.identifier.urihttp://hdl.handle.net/2117/21071
dc.description.abstractIn this paper we develop combinatorial methods for the evaluation of yield and operational reliability of fault-tolerant systems-on-chip. The method for yield computation assumes that defects are produced according to a model in which defects are lethal and affect given components of the system following a distribution common to all defects; the method for the computation of operational reliability also assumes that the fault-tree function of the system is increasing. The distribution of the number of defects is arbitrary. The methods are based on the formulation of, respectively, the yield and the operational reliability as the probability that a given boolean function with multiple-valued variables has value 1. That probability is computed by analyzing a ROMDD (reduced ordered multiple-value decision diagram) representation of the function. For efficiency reasons, a coded ROBDD (reduced ordered binary decision diagram) representation of the function is built first and, then, that coded ROBDD is transformed into the ROMDD required by the methods. We present numerical experiments showing that the methods are able to cope with quite large systems in moderate CPU times.
dc.format.extent12 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshIntegrated circuits -- Very large scale integration -- Tests
dc.titleCombinatorial methods for the evaluation of yield and operational reliability of fault-tolerant systems-on-chip
dc.typeArticle
dc.subject.lemacCircuits integrats a molt gran escala -- Tests
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.rights.accessOpen Access
local.identifier.drac672998
dc.description.versionPostprint (published version)
local.citation.authorCarrasco, J.; Suñe, V.
local.citation.publicationNameMicroelectronics reliability
local.citation.volume44
local.citation.number2
local.citation.startingPage339
local.citation.endingPage350


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