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Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes
dc.contributor.author | Lorente, Vicente |
dc.contributor.author | Valero, Alejandro |
dc.contributor.author | Sahuquillo, Julio |
dc.contributor.author | Petit, Salvador |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | López, Pedro |
dc.contributor.author | Duato, José |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2013-11-11T10:33:14Z |
dc.date.created | 2013 |
dc.date.issued | 2013 |
dc.identifier.citation | Lorente, V. [et al.]. Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. A: Design, Automation and Test in Europe. "Design, Automation & Test in Europe: Grenoble, France, March 18-22, 2013: proceedings". Grenoble: 2013, p. 83-88. |
dc.identifier.isbn | 978-1-4673-5071-6 |
dc.identifier.uri | http://hdl.handle.net/2117/20567 |
dc.description.abstract | Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages below Vccmin. Recent proposals provide a rather low fault-coverage due to the fault coverage/overhead trade-off. We propose a new fault- tolerant L1 cache, which combines SRAM and eDRAM cells in L1 data caches to provide 100% SRAM hard-error fault coverage. Results show that, compared to a conventional cache and assuming 50% failure probability at low-power mode, leakage and dynamic energy savings are by 85% and 62%, respectively, with a minimal impact on performance. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Information storage and retrieval systems |
dc.subject.lcsh | Cache memory |
dc.subject.other | Memory |
dc.subject.other | DRAM |
dc.subject.other | SRAM |
dc.title | Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes |
dc.type | Conference report |
dc.subject.lemac | Informació -- Sistemes d'emmagatzematge i recuperació |
dc.subject.lemac | Memòria cau |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.7873/DATE.2013.031 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://dx.doi.org/10.7873/DATE.2013.031 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 12730960 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS |
dc.date.lift | 10000-01-01 |
local.citation.author | Lorente, V.; Valero, A.; Sahuquillo, J.; Petit, S.; Canal, R.; López, P.; Duato, J. |
local.citation.contributor | Design, Automation and Test in Europe |
local.citation.pubplace | Grenoble |
local.citation.publicationName | Design, Automation & Test in Europe: Grenoble, France, March 18-22, 2013: proceedings |
local.citation.startingPage | 83 |
local.citation.endingPage | 88 |