A self-adaptive hardware architecture with fault tolerance capabilities
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This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other adaptive capabilities of the system are self-routing, self-placement and runtime self-configuration. Additionally, it is described as an example application and a software tool that has been implemented to facilitate the development of applications to test the system.
CitacióSoto, J.; Moreno, J.; Cabestany, J. A self-adaptive hardware architecture with fault tolerance capabilities. "Neurocomputing", 09 Desembre 2013, vol. 121, p. 25-31.
Versió de l'editorhttp://www.sciencedirect.com/science/article/pii/S0925231213004293
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