Physical planning for the architectural exploration of large-scale chip multiprocessors

Abstract

This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout constraints that enforce regularity in the interconnect networks. Routing is performed on top of memories and components that underutilize the available metal layers for interconnectivity. The experiments demonstrate the impact of physical parameters in the selection of the most efficient architectures. Thus, the integrated flow contributes to deliver physically-viable architectures and simplify the complex design closure of large-scale CMPs.