CMOS fast transient low-dropout regulator
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
In this paper a fast transient response CFA-based low-dropout regulator (LDO) is introduced. The circuit is stable for 0-100mA output load current and a 1μF output capacitor without any internal compensation. The CFA consists of a voltage follower with output local current-current feedback based on a level-shifted flipped voltage follower (LSFVF) which is instrumental to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the pass transistor results in high PSRR. Full transistor-level simulation results for an AMS 0.35μm CMOS process design reveal that the proposed LDO dissipates 58μA quiescent current at no-load condition and in worst case conditions has a current efficiency of 99.8%. For a 1μF output capacitor, the maximum output voltage variation to a 0-100mA load transient with rise and fall time of 10 and 100ns is only 2.5mV, and the PSRR is smaller than -58dB over the entire load current range.
CitationSaberkari, A.; Alarcon, E.; Shokouhi, S. CMOS fast transient low-dropout regulator. A: Iranian Conference Electrical Engineering. "20th Iranian Conference on Electrical Engineering (ICEE) 2012: 15-17 May 2012: Tehran, Iran". Tehran: Institute of Electrical and Electronics Engineers (IEEE), 2012, p. 105-108.
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