A Novel variation-tolerant 4T-DRAM with enhance soft-error tolerance
Document typeConference report
Rights accessRestricted access - publisher's policy
In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment.
CitationGanapathy, S. [et al.]. A Novel variation-tolerant 4T-DRAM with enhance soft-error tolerance. A: IEEE International Conference on Computer Design. "30th International Conference on Computer Design (ICCD)". Montreal, Québec: IEEEXPLORE, 2012, p. 472-477.
- ARCO - Microarquitectura i Compiladors - Ponències/Comunicacions de congressos 
- HIPICS - High Performance Integrated Circuits and Systems - Ponències/Comunicacions de congressos 
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos 
- Departament d'Enginyeria Electrònica - Ponències/Comunicacions de congressos