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Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.author | Amat Bertran, Esteve |
dc.contributor.author | Pouyan, Peyman |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2012-09-26T10:59:55Z |
dc.date.created | 2012 |
dc.date.issued | 2012 |
dc.identifier.citation | Rubio, J.A.; Amat, E.; Pouyan, P. Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime. A: VLSI Test Symposium. "Proceedings of the VLSI Test Symposium". Hawaii: IEEE Press. Institute of Electrical and Electronics Engineers, 2012, p. 240-245. |
dc.identifier.uri | http://hdl.handle.net/2117/16582 |
dc.description.abstract | Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded SRAM memories. This work introduces a novel version that modifies and enhances the advantages of this method by considering the process variability impact on the memory components. Our results show between 30% and 45% SRAM lifetime increases over the existing proactive reconfiguration technique and between 1.7X and ~10X improvement over the non-proactive reconfiguration. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | IEEE Press. Institute of Electrical and Electronics Engineers |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
dc.subject.lcsh | Electronic circuit design -- Fiabilitat |
dc.title | Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime |
dc.type | Conference lecture |
dc.subject.lemac | Circuits electrònics -- Reliability |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6231060 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 10680614 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Rubio, J.A.; Amat, E.; Pouyan, P. |
local.citation.contributor | VLSI Test Symposium |
local.citation.pubplace | Hawaii |
local.citation.publicationName | Proceedings of the VLSI Test Symposium |
local.citation.startingPage | 240 |
local.citation.endingPage | 245 |