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Vectorized register tiling
dc.contributor.author | Berna Juan, Alejandro |
dc.contributor.author | Jiménez Castells, Marta |
dc.contributor.author | Llaberia Griñó, José M. |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2012-07-20T15:21:50Z |
dc.date.available | 2012-07-20T15:21:50Z |
dc.date.created | 2012-01 |
dc.date.issued | 2012-01 |
dc.identifier.citation | Berna, A.; Jimenez, M.; Llaberia, J. "Vectorized register tiling". 2012. |
dc.identifier.uri | http://hdl.handle.net/2117/16308 |
dc.description.abstract | In the last years, there has been much effort in commercial compilers (icc, gcc) to exploit efficiently the SIMD capabilities and the memory hierarchy that the current processors offer. However, the small numbers of compilers that can automatically exploit these characteristics achieve in most cases unsatisfactory results. Therefore, the programmers often need to apply by hand the optimizations to the source code, write manually the code in assembly or use compiler built-in functions (such intrinsics) to achieve high performance. In this work, we present source-to-source transformations that help commercial compilers exploiting the memory hierarchy and generating efficient SIMD code. Results obtained on our experiments show that our solutions achieve as excellent performance as hand-optimized vendor-supplied numerical libraries (written in assembly). |
dc.format.extent | 2 p. |
dc.language.iso | eng |
dc.relation.ispartofseries | UPC-DAC-RR-CAP-2012-4 |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Programació |
dc.subject.lcsh | Parallel programming (Computer science) |
dc.title | Vectorized register tiling |
dc.type | External research report |
dc.subject.lemac | Programació en paral·lel (Informàtica) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://www.ac.upc.edu/app/research-reports/html/2012/5/abstractAndPoster.pdf |
dc.rights.access | Open Access |
local.identifier.drac | 9638077 |
dc.description.version | Preprint |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
local.citation.author | Berna, A.; Jimenez, M.; Llaberia, J. |
local.citation.publicationName | Vectorized register tiling |
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