Reconfigurable memory controller with programmable pattern support
Document typeConference report
Rights accessRestricted access - publisher's policy
Heterogeneous architectures are increasingly popular due to their flexibility and high performance per watt capability. A kind of heterogeneous architecture, reconfigurable systems-on-chip, offer high performance per watt through the reconfigurable logic and flexibility via multiprocessor cores. But in order to achieve the performance goals it is necessary to provide enough data to the accelerators. In this paper we describe a programmable, pattern-based memory controller (PMC) that aims at improving the performance of heterogeneous or reconfigurable SoC devices. These include scatter gather and strided 1D, 2D and 3D patterns. PMC can prefetch complete patterns into scratchpads that can then be accessed either by a microprocessor or by an accelerator. As a result, the microprocessors and accelerators can focus on computation and are relieved of having to perform address calculations. PMC has been implemented and tested on an ML505 evaluation board using the MicroBlaze softcore as the platform’s microprocessor. While PMC adds some latency, it improves performance by offloading the processor and by making better use of available bandwidths. The PMC provide 1.5x speed-ups with processor and 27x speed-ups achieved by using hardware accelerator in PMC SoC based environment while executing thresholding application.
CitationHussain, T.; Pericas, M.; Ayguade, E. Reconfigurable memory controller with programmable pattern support. A: HiPEAC Workshop on Reconfigurable Computing. "5th HiPEAC Workshop on Reconfigurable Computing: WRC 2011: 23 January 2011, Heraklion, Crete, Greece". Heraklion, Creta: 2011, p. 55-65.
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