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Integrating dataflow abstractions into transactional memory
dc.contributor.author | Gajinov, Vladimir |
dc.contributor.author | Milovanovic, Milos |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2012-07-09T16:33:27Z |
dc.date.created | 2011 |
dc.date.issued | 2011 |
dc.identifier.citation | Gajinov, V. [et al.]. Integrating dataflow abstractions into transactional memory. A: Workshop on Systems for Future Multi-Core Architectures. "First Workshop on Systems for Future Multi-Core Architectures". Salzburg: 2011, p. 1-7. |
dc.identifier.uri | http://hdl.handle.net/2117/16218 |
dc.description.abstract | Many concurrent programs require some form of conditional synchronization to coordinate the execution of different program tasks. Programming these algorithms using transactional memory (TM) often results in a high conflict rate between transactions. In this paper we propose an Atomic dataflow model - ADF, which aims to reduce transaction conflicts by incorporating dataflow scheduling principles into transactional memory. The ADF model is based on the execution of atomic units of work called ADF tasks. A programmer explicitly defines data dependencies for the ADF task using the trigger set extension. Trigger set data is implicitly tracked by the TM runtime system, which detects changes and enables the re-execution of a transaction when its dependencies are satisfied. In this paper we fully describe the ADF model, present its syntax and show advantages of the model on a practical example. |
dc.format.extent | 7 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Programació |
dc.subject.lcsh | Parallel programming (Computer science) |
dc.title | Integrating dataflow abstractions into transactional memory |
dc.type | Conference report |
dc.subject.lemac | Programació en paral·lel (Informàtica) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 9602542 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Gajinov, V.; Milovanovic, M.; Unsal, O.; Cristal-Kestelman, A.; Ayguade, E.; Valero, M. |
local.citation.contributor | Workshop on Systems for Future Multi-Core Architectures |
local.citation.pubplace | Salzburg |
local.citation.publicationName | First Workshop on Systems for Future Multi-Core Architectures |
local.citation.startingPage | 1 |
local.citation.endingPage | 7 |