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dc.contributor.authorGajinov, Vladimir
dc.contributor.authorMilovanovic, Milos
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2012-07-09T16:33:27Z
dc.date.created2011
dc.date.issued2011
dc.identifier.citationGajinov, V. [et al.]. Integrating dataflow abstractions into transactional memory. A: Workshop on Systems for Future Multi-Core Architectures. "First Workshop on Systems for Future Multi-Core Architectures". Salzburg: 2011, p. 1-7.
dc.identifier.urihttp://hdl.handle.net/2117/16218
dc.description.abstractMany concurrent programs require some form of conditional synchronization to coordinate the execution of different program tasks. Programming these algorithms using transactional memory (TM) often results in a high conflict rate between transactions. In this paper we propose an Atomic dataflow model - ADF, which aims to reduce transaction conflicts by incorporating dataflow scheduling principles into transactional memory. The ADF model is based on the execution of atomic units of work called ADF tasks. A programmer explicitly defines data dependencies for the ADF task using the trigger set extension. Trigger set data is implicitly tracked by the TM runtime system, which detects changes and enables the re-execution of a transaction when its dependencies are satisfied. In this paper we fully describe the ADF model, present its syntax and show advantages of the model on a practical example.
dc.format.extent7 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Programació
dc.subject.lcshParallel programming (Computer science)
dc.titleIntegrating dataflow abstractions into transactional memory
dc.typeConference report
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac9602542
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorGajinov, V.; Milovanovic, M.; Unsal, O.; Cristal-Kestelman, A.; Ayguade, E.; Valero, M.
local.citation.contributorWorkshop on Systems for Future Multi-Core Architectures
local.citation.pubplaceSalzburg
local.citation.publicationNameFirst Workshop on Systems for Future Multi-Core Architectures
local.citation.startingPage1
local.citation.endingPage7


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