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Hardware/software-based diagnosis of load-store queues using expandable activity logs
dc.contributor.author | Carretero Casado, Javier Sebastián |
dc.contributor.author | Vera Rivera, Francisco Javier |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Ramírez García, Tanausu |
dc.contributor.author | Monchiero, Matteo |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2012-03-22T14:35:06Z |
dc.date.available | 2012-03-22T14:35:06Z |
dc.date.created | 2011 |
dc.date.issued | 2011 |
dc.identifier.citation | Carretero, J. [et al.]. Hardware/software-based diagnosis of load-store queues using expandable activity logs. A: International Symposium on High-Performance Computer Architecture (HPCA). "Proceedings 17th IEEE International Symposium on High Performance Computer Architecture". San Antonio, Texas: IEEE Press. Institute of Electrical and Electronics Engineers, 2011, p. 321-332. |
dc.identifier.uri | http://hdl.handle.net/2117/15652 |
dc.description.abstract | The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing speeds are common limitations in current testing techniques. Moreover, low observability defies full-speed testing approaches. Modern solutions like on-chip trace buffers alleviate these issues, but are unable to store long activity traces. As a consequence, the cost of post-Si validation now represents a large fraction of the total design cost. This work describes a hybrid post-Si approach to validate a modern load-store queue. We use an effective error detection mechanism and an expandable logging mechanism to observe the microarchitectural activity for long periods of time, at processor full-speed. Validation is performed by analyzing the log activity by means of a diagnosis algorithm. Correct memory ordering is checked to root the cause of errors. |
dc.format.extent | 12 p. |
dc.language.iso | eng |
dc.publisher | IEEE Press. Institute of Electrical and Electronics Engineers |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Fault detection and isolation (Control enigeering) |
dc.subject.lcsh | Program verification |
dc.subject.lcsh | Computer architecture |
dc.title | Hardware/software-based diagnosis of load-store queues using expandable activity logs |
dc.type | Conference report |
dc.subject.lemac | Programari -- Control de qualitat |
dc.subject.lemac | Arquitectura d'ordinadors |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/HPCA.2011.5749740 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5749740 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 9463774 |
dc.description.version | Postprint (published version) |
local.citation.author | Carretero, J.; Vera, F.; Abella, J.; Ramirez, T.; Monchiero, M.; González, A. |
local.citation.contributor | International Symposium on High-Performance Computer Architecture (HPCA) |
local.citation.pubplace | San Antonio, Texas |
local.citation.publicationName | Proceedings 17th IEEE International Symposium on High Performance Computer Architecture |
local.citation.startingPage | 321 |
local.citation.endingPage | 332 |