Hardware/software-based diagnosis of load-store queues using expandable activity logs
Document typeConference report
PublisherIEEE Press. Institute of Electrical and Electronics Engineers
Rights accessRestricted access - publisher's policy
The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing speeds are common limitations in current testing techniques. Moreover, low observability defies full-speed testing approaches. Modern solutions like on-chip trace buffers alleviate these issues, but are unable to store long activity traces. As a consequence, the cost of post-Si validation now represents a large fraction of the total design cost. This work describes a hybrid post-Si approach to validate a modern load-store queue. We use an effective error detection mechanism and an expandable logging mechanism to observe the microarchitectural activity for long periods of time, at processor full-speed. Validation is performed by analyzing the log activity by means of a diagnosis algorithm. Correct memory ordering is checked to root the cause of errors.
CitationCarretero, J. [et al.]. Hardware/software-based diagnosis of load-store queues using expandable activity logs. A: International Symposium on High-Performance Computer Architecture (HPCA). "Proceedings 17th IEEE International Symposium on High Performance Computer Architecture". San Antonio, Texas: IEEE Press. Institute of Electrical and Electronics Engineers, 2011, p. 321-332.