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An abstraction methodology for the evaluation of multi-core multi-threaded architectures
dc.contributor.author | Zilan, Ruken |
dc.contributor.author | Verdú Mulà, Javier |
dc.contributor.author | García Vidal, Jorge |
dc.contributor.author | Nemirovsky, Mario |
dc.contributor.author | Milito, Rodolfo |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2012-02-27T12:31:37Z |
dc.date.available | 2012-02-27T12:31:37Z |
dc.date.created | 2011 |
dc.date.issued | 2011 |
dc.identifier.citation | Zilan, Ruken [et al.]. An abstraction methodology for the evaluation of multi-core multi-threaded architectures. A: IEEE/ACM International Symposium on Modelling, Analysis and Simulation of Computer and Telecommunication Systems. "Proceedings of 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)". IEEE Computer Society Publications, 2011, p. 478-481. |
dc.identifier.isbn | 978-1-4577-0468-0 |
dc.identifier.uri | http://hdl.handle.net/2117/15378 |
dc.description.abstract | As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to execute the large amount of experiments required to obtain indicative results. To achieve a thorough analysis of the system, software benchmarks or traces are required. In many cases when an analysis is needed most, during the earlier stages of the processor design, benchmarks or traces are not available. Analytical models overcome these limitations but do not provide the fine grain details needed for a deep analysis of these architectures. In this work we present a new methodology to abstract processor architectures, at a level between cycle-accurate and analytical simulators. To apply our methodology we use queueing modeling techniques. Thus, we introduce Q-MAS, a queueing based tool targeting a real chip (the Ultra SPARC T2 processor) and aimed at facilitating the quantification of trade-offs during the design phase of multi-core multi-threaded processor architectures. The results demonstrate that Q-MAS, the tool that we developed, provides accurate results very close to the actual hardware, with a minimal cost of running what-if scenarios. |
dc.format.extent | 4 p. |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society Publications |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject.lcsh | Performance evaluation |
dc.subject.lcsh | Multiprocessing systems |
dc.subject.lcsh | Parallel architectures |
dc.subject.lcsh | Microprocessors chips |
dc.title | An abstraction methodology for the evaluation of multi-core multi-threaded architectures |
dc.type | Conference report |
dc.subject.lemac | Arquitectura d'ordinadors |
dc.contributor.group | Universitat Politècnica de Catalunya. CNDS - Xarxes de Computadors i Sistemes Distribuïts |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/MASCOTS.2011.11 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6005400 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 9454973 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
local.citation.author | Zilan, Ruken; Verdu, J.; García, J.; Nemirovsky, M.; Milito, R.; Valero, M. |
local.citation.contributor | IEEE/ACM International Symposium on Modelling, Analysis and Simulation of Computer and Telecommunication Systems |
local.citation.publicationName | Proceedings of 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) |
local.citation.startingPage | 478 |
local.citation.endingPage | 481 |