Simultaneous switching noise has become an important issue due to its signal integrity and timing implications.
Therefore a lot of time and resources are spent during the PDN design to minimize the supply voltage variation. This paper presents the self-adaptive clock as an alternative to tolerate the critical path delay variation due to supply noise thanks to its self-adaptable nature. A self-adaptive clock generation circuit is
proposed in this paper and its benefits, in terms of clock period reduction, are assessed under a realistic supply noise obtained through simulation for different switching activities.
CitationJ. Pérez-Puigdemont; Moll, F.; Cortadella, J. Measuring the tolerance of self-adaptive clocks to supply voltage noise. A: Conference on Design of Circuits and Integrated Systems. "26th Conference on Design of Circuits and Integrated Systems : the next 25 years". Albufeira: 2011, p. 399-404.
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