Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is
why regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Our
objective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-Ripple
Adders from 4 bits to 64 bits.
CitationPons, M.; Moll, F.; Rubio, A.; Abella, J.; Vera, X.; González, A. Via-configurable transistor array: a regular design technique to improve ICs yield. 2nd IEEE International Workshop on Design for Manufacturability and Yield 2007; IEEE International Test Conference, October 25-26, 2007.
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