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This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other self-adaptive capabilities of the system are self-routing, self-placement and runtime self-configuration.
CitationSoto, J.; Moreno, J.; Cabestany, J. Description of a fault tolerance system implemented in a hardware architecture with self-adaptive capabilities. A: International Work-Conference on Artificial Neural Networks. "11th International Work-Conference on Artificial Neural Networks". Torremolinos: Springer Verlag, 2011, p. 557-564.
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