Implementing a hybrid SRAM / eDRAM NUCA architecture

dc.contributor.author	Lira Rueda, Javier
dc.contributor.author	Molina Clemente, Carlos
dc.contributor.author	Brooks, David
dc.contributor.author	González Colás, Antonio María
dc.contributor.other	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned	2011-11-16T11:21:21Z
dc.date.available	2011-11-16T11:21:21Z
dc.date.issued	2010-08-27
dc.identifier.uri	http://hdl.handle.net/2117/13932
dc.description.abstract	In this paper, we propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. We demonstrate, that due to the high locality found in emerging applications, a high percentage of data that enters to the on-chip last-level cache are not accessed again before they are replaced
dc.format.extent	10 p.
dc.language.iso	eng
dc.relation.ispartofseries	UPC-DAC-RR-ARCO-2010-3
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcsh	SRAM chips
dc.subject.lcsh	NUCA cache
dc.subject.lcsh	eDRAM module
dc.title	Implementing a hybrid SRAM / eDRAM NUCA architecture
dc.type	External research report
dc.subject.lemac	SRAM chips
dc.subject.lemac	DRAM chips
dc.contributor.group	Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.rights.access	Open Access
local.identifier.drac	5354088
dc.description.version	Preprint
local.personalitzacitacio	true

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