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Environmental conditions are changing all the time along the chip as a consequence of its own activity, provoking deviations on propagation time in digital circuits. In future technologies, the increment of devices sensitivity to environmental
fluctuations yields to a wider range of possible time deviations, being for example, in an NOT gate designed in a 16nm technology
1.6 times larger than for a 45nm version. But this ratio is different for every circuit cause it depends on its fundamental
structure and characteristics. In this paper the tendency of timing parameters deviations due to environmental factors fluctuation
and how these deviations have deeper impact on more complex structures are analyzed. It is shown that the internal structure of the logic gates cause a mismatch between logic circuits and in future technologies it will be enlarged.
CitationAndrade, D. [et al.]. Analysis of delay mismatching of digital circuits caused by common environmental fluctuations. A: IEEE International Symposium on Circuits and Systems. "2011 IEEE International Symposium on Circuits and Systems". Rio de Janeiro: IEEE, 2011, p. 2585-2588.
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