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Light NUCA: a proposal for bridging the inter-cache latency gap
dc.contributor.author | Suárez, Dario |
dc.contributor.author | Monreal Arnal, Teresa |
dc.contributor.author | Vallejo, Fernando |
dc.contributor.author | Beivide Palacio, Julio Ramón |
dc.contributor.author | Viñals Yufera, Víctor |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2011-09-21T13:54:46Z |
dc.date.available | 2011-09-21T13:54:46Z |
dc.date.created | 2009 |
dc.date.issued | 2009 |
dc.identifier.citation | Suárez, D. [et al.]. Light NUCA: a proposal for bridging the inter-cache latency gap. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe 2009". Nice: IEEE Computer Society, 2009, p. 530-535. |
dc.identifier.uri | http://hdl.handle.net/2117/13287 |
dc.description.abstract | To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). Recently, Non-Uniform Cache Architectures (NUCAs) have been proposed to sustain the size growth trend of secondary caches that is threatened by wire-delay problems. NUCAs are size-oriented, and they were not conceived to close the inter-cache latency gap. To tackle this problem, we propose Light NUCAs (L-NUCAs) leveraging on-chip wire density to interconnect small tiles through specialized networks, which convey packets with distributed and dynamic routing. Our design reduces the tile delay (cache access plus one-hop routing) to a single processor cycle and places cache lines at a finer-granularity than conventional caches reducing cache latency. Our evaluations show that in general, L-NUCA improves simultaneously performance, energy, and area when integrated into both conventional or D-NUCA hierarchies. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Computer storage devices |
dc.subject.other | Non-uniform cache architectures |
dc.subject.other | NUCAs |
dc.subject.other | Light NUCAs |
dc.subject.other | L-NUCAs |
dc.title | Light NUCA: a proposal for bridging the inter-cache latency gap |
dc.type | Conference lecture |
dc.subject.lemac | Ordinadors -- Memòries |
dc.rights.access | Open Access |
local.identifier.drac | 2452375 |
dc.description.version | Postprint (author’s final draft) |
local.citation.author | Suárez, D.; Monreal, T.; Vallejo, F.; Beivide, R.; Viñals, V. |
local.citation.contributor | Design, Automation and Test in Europe |
local.citation.pubplace | Nice |
local.citation.publicationName | Design, Automation and Test in Europe 2009 |
local.citation.startingPage | 530 |
local.citation.endingPage | 535 |