Hardware customization for scientific applications has shown a big potential for reducing power consumption and increasing performance. In particular, the automatic generation of ISA extensions for General-Purpose Processors (GPPs) to accelerate domain-specific applications is an active field of research. Those domain-specific customized processors are mostly evaluated in simulation environments due to technical and programmability issues while using real hardware. There is no automatic mechanism to test ISA extensions in a real hardware environment. In this paper we present a toolchain that can automatically identify
candidate parts of the code suitable for acceleration to test them in a reconfigurable hardware.
We validate our toolchain using a bioinformatic application, ClustalW, obtaining an overall speed-up over 2x.
CitationGonzález, C. [et al.]. Preliminary work on a mechanism for testing a customized architecture. A: International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems. "5th Advanced Computer Architecture and Compilation for Embedded Systems". 2009.
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder. If you wish to make any use of the work not provided for in the law, please contact: email@example.com